Multi-phase Synchronous Buck Converter
Overview
This demo model, as seen in Fig. 1, shows a configurable multi-phase synchronous buck converter with a load step.
Fig. 1 Multi-phase synchronous buck converter
Note
Model
Power Circuit
A description of the synchronous buck converter topology is given in the demo model Synchronous Buck Converter. In this model, a \(12\,\mathrm{V}\) input is stepped down to \(5\,\mathrm{V}\) at the output. Initially, there is a \(2.5\,\Omega\) resistive load present, but then a parallel \(2.5\,\Omega\) load is switched in, effectively halving the load resistance. The switching cell can be paralleled in multiple phases, which is a common technique to reduce the stress on the devices and ripple currents.
This model features the Wire Selector component and a dynamic subsystem mask to implement and appropriately display a user-specified number of buck converter phases. The number of phases may be varied within the subsystem mask to automatically create an equivalent number of parallel connections of blocks contained between the input and output Wire Selector components. Fig. 2 shows an example image of the effective switching cell topology when \(3\) phases are specified.
Fig. 2 Switching cell
The dynamic mask feature is new in PLECS 4.2 and varies the icon depending on the specified number of phases. Within the switching cell subsystem’s mask, drawing functions are implemented in the Lua language to display an icon showing an appropriate number of half bridges. Additionally, the modulator uses phase shift logic to properly account for the number of phases selected by the user.
Controls
The switch modulation is generated by comparing the modulation index, provided via feedback control, with the output of a Triangular Wave Generator block. The output voltage is measured and compared with a \(5\,\mathrm{VDC}\) set point. Nested voltage and current PI control loops are used to determine the duty cycle of the FETs. For the current feedback, a voltage measurement is made across a current sensing resistor rather than an ideal ammeter block to account for its associated impedance. The control signal is scaled by a factor of this resistance to effectively convert the voltage measurement into amperes. The gain parameters of the controller are adjusted automatically depending on the switching frequency, output capacitance and resistance. The duty cycle range is limited between \(1\,\%\) and \(99\,\%\), and logic is included to prevent windup of the integrator. The two switches in each phase are then modulated in a complementary manner. In practice, it is important not to gate both switches on at the same time to avoid shoot-through. This is prevented by introducing a dead time to delay the turn-on of the opposing switches. Also, the individual phase currents are averaged over one period and subtracted from the current set point in an effort to reduce the inductor current offset and achieve balancing across the phase inductors.
Simulation
Run the simulation with the model as provided to view the output signals and individual inductor currents. The simulation includes the start-up of the converter as well as a load step demonstrating the controller response. Try comparing a few simulations with an increasing number of phases - you should be able to observe reduced individual phase current averages and ripple magnitudes, resulting in reduced strain on the individual switches.