Single-Phase Battery Charger

Overview

This demonstration shows a grid-connected battery charger with cascaded AC/DC and DC/DC converters. The AC/DC converter is regulated by a digital PI controller to achieve power factor correction (PFC) and maintain the DC bus voltage at \(300\,\mathrm{VDC}\). The DC/DC converter is designed to provide a maximum \(120\,\mathrm{VDC}\) output at a power rating of \(1.4\,\mathrm{kW}\).

Fig. 1 Top-level schematic of the model.

Note

This model contains model initialization commands that are accessible from:

PLECS Standalone: the menu Simulation > Simulation Parameters… > Initializations

PLECS Blockset: right click in the Simulink model window > Model Properties > Callbacks > InitFcn*

Model

AC/DC Converter

The AC/DC converter is connected on the AC side via a single stage low pass filter. The topology is an interleaved PFC boost converter, as described in Microchip’s application note (AN1278) [1].

Digital control loops for voltage and current regulation are implemented to achieve power factor correction and regulate the DC side voltage to a desired level. The DC side voltage is sampled and compared to the target bus voltage setpoint. The digital voltage compensator with anti-windup sets a DC current setpoint. This DC setpoint is converted into an AC current setpoint to achieve PFC. The current compensator determines a voltage setpoint, which is converted to a duty cycle. The duty cycle is then used by two symmetrical interleaved PWM blocks.

Fig. 2 Schematic of the AC/DC converter.

DC/DC Converter

The DC/DC converter implementation is based on a phase-shifted resonant converter, as described in the PLECS demo model Phase Shift DC-DC Converter with Integrated Magnetics [2].

Fig. 3 Schematic of the DC/DC converter.

Thermal Model

A thermal description is assigned to all four of the MOSFET switches in the full bridge as well as the output diodes. These descriptions can be viewed and edited by double-clicking on the component and selecting Edit… from the drop-down menu of the Thermal description parameter. The thermal parameters were obtained from datasheets, specifically for the On Semiconductor’s SupreMOS superjunction MOSFET and Infineon’s IDW75E60 Si power diode. For the two different device types, the thermal impedance chain representing the thermal transitions from the junction to the case are entered directly in the thermal descriptions.

Each switch (Q1-Q4) in the H-bridge converter is realized using three MOSFETs connected in parallel. The number of parallel devices is configured in the parameter window. An equal distribution of current is assumed across all parallel devices, and the thermal parameters are automatically scaled to reflect the device count and configuration.

Since the three heat sink components are connected together, all six devices dissipate heat into the same heat sink. A thermal resistance connects the heat sink with the temperature of the ambient air. The thermal descriptions for the MOSFETs and diodes are stored in a private thermal library in the directory /single_phase_battery_charger_plecs.

Simulation

Run the simulation with the model as provided to view the grid side, bus capacitor, and load voltage waveforms. The AC/DC converter is regulated to maintain the bus voltage at \(300\,\mathrm{VDC}\).

Fig. 4 Simulated DC link voltage.

Initially the output voltage is regulated to \(96\,\mathrm{VDC}\), and at \(t=0.2\,\mathrm{s}\), the output reference voltage is stepped to \(120\,\mathrm{VDC}\). This voltage step change causes the bus capacitor to sag as it is discharged to provide increased load current. The voltage is regulated back to the \(300\,\mathrm{VDC}\) setpoint by the AC/DC converter. The bus capacitor voltage can be seen in the “DC Bus” plot, shown above. At \(t=0.35\,\mathrm{s}\), the output reference voltage is maintained at \(120\,\mathrm{VDC}\) and the load is doubled. The bus capacitor is again discharged by the increase in load current. The output current and voltage can be seen in the “Output” plot Fig. 5. The AC/DC and DC/DC converter result in PFC, as can be seen in the “AC Input” plot Fig. 6.

Fig. 5 Simulated output characteristics.

Fig. 6 Simulated grid characteristics.

Conclusion

This demo model shows a grid-connected battery charger with cascaded AC/DC and DC/DC converters. The system is controlled in each stage with cascaded control loops for current and voltage. The DC/DC converter is realized with a phase-shifted resonant converter and it’s thermal behavior is analyzed using the PLECS thermal domain. The magnetic characteristic of the two parallel E70/33/32 cores is implemented with magnetic components from the PLECS component library such as Air Gaps and Linear Permeances. This way different system level optimization goals such as weight (considering magnetics), losses (considering thermal aspects) and stability can be analyzed and traded off against each other.

Bibliography

[1]

V. Skanda and A. Nahar, Interleaved Power Factor Correction (IPFC) Using the dsPIC DSC, DS01278A, Microchip Technology, 2009.

[2]

U. Badstuebner and J. Biela and B. Faessler and D. Hoesli and J.W. Kolar, An Optimized 5 kW, \(147\,W/in^3\) Telecom Phase-Shift DC-DC Converter with Magnetically Integrated Current Doubler, Applied Power Electronics Conference and Exposition (APEC), 2009, Twenty-Seventh Annual IEEE, pp. 21-27, 15-19 Feb. 2009.