D Flip-flop
Purpose
Implement edge-triggered flip-flop
Library
Control / Logical
Description
The D flip-flop sets its output Q to the value of its input D when an edge on the clock input is detected. The behavior is shown in the following truth table:
D |
Clk |
Q |
/Q |
|---|---|---|---|
0 |
0 |
No change |
No change |
0 |
1 |
No change |
No change |
1 |
0 |
No change |
No change |
1 |
1 |
No change |
No change |
0 |
Triggering edge |
0 |
1 |
1 |
Triggering edge |
1 |
0 |
The input D is latched, i.e. when a triggering edge in the clock signal is detected the value of D from the previous simulation step is used to set the output. In other words, D must be stable for at least one simulation step before the flip-flop is triggered by the clock signal.
Parameters
- Trigger edge
The direction of the edge on which the D input is read.
- Initial state
The state of the flip-flop at simulation start.
Probe Signals
- D
The input signal D.
- Clk
The clock input signal.
- Q
The output signals Q.
- /Q
The output signals /Q.