Full Bridges (Series Connected)
Purpose
Series-connected full-bridge inverters
Library
Electrical / Power Modules
Description
This component implements multiple series-connected inverter cells for use in modular multilevel converters. All control signals as well as the DC side terminals are vectorized with their width matching the number of cells. The component offers two configurations:
- Switched
All power semiconductors are modeled with ideal switches. The individual switches are controlled with logical gate signals. A switch is on if the corresponding gate signal is not zero. For compatibility with the averaged configuration it is recommended to use the value \(1\) for non-zero gate signals.
- Sub-cycle average
The component as a whole is modeled with controlled voltage and current sources. The DC sides of the inverter cells have current source behavior and and must be connected to positively biased capacitors or voltage sources. The DC sides must remain galvanically isolated from each other. The AC sides are typically connected to an inductor. The control inputs are the relative on-times of the switches with values between \(0\) and \(1\).
In the average configuration the inverters can be operated in two ways:
The control signals are instantaneous logical gate signals having the values \(0\) and \(1\).
The control signals are the duty cycles of the individual switches. They are either computed directly from the modulation index or by periodically averaging the digital gate signal over a fixed period of time, e.g. using the Periodic Average block. The averaging period does not need to be synchronized with the PWM and can be as large as the inverse of the switching frequency.
In both use cases, the average implementation correctly accounts for blanking times, i.e. when during commutation both switches in one inverter leg are turned off. It also supports discontinuous conduction mode, e.g. when charging the DC link capacitors via the reverse diodes.
Since the duty cycle is simulated accurately even with relatively large time steps, the average configuration is particularly well suited for real-time simulations with high switching frequencies. It can also increase the speed of offline simulations, because the number of internal switches is greatly reduced.
The sub-cycle average model implementation requires an internal switching element on the AC side. When generating code for the power module the switching element is modeled as either an ideal or non-ideal switch. See Ideal and Non-Ideal Switch Models in Electric Circuits for detailed descriptions of the switch model implementations.
Note
The sub-cycle average implementation cannot model a shoot-through, i.e. the situation where both switches in a leg are turned on at the same time. Therefore, the sum of the control signals for the upper and lower switch in a leg must not exceed \(1\) at any time. Since the DC sides are not clamped, the DC voltages must never become negative.
Parameters
- Configuration
Switched or averaged circuit model.
- Semiconductor symbol
This setting lets you choose between
IGBTandMOSFETfor the symbol the active semiconductor switches. This setting does not change the electrical behavior of the power module in simulation.- Number of cells
Number of series-connected full-bridge inverters.
- Assertions
When set to
on, the block will flag an error if the sum of the control signals for the upper and lower switch in a leg exceeds \(1\).- Switch model (CPU code generation)
Select the switch model in the generated code.