5-Level Half Bridge (ANPC)

Purpose

5-level active neutral-point clamped half-bridge converter module

Library

Electrical / Power Modules

Description

../../_images/powermodule_5level_anpc.svg

This power module implements a single leg of a 5-level active neutral-point clamped voltage source converter. It contains eight switches S1 to S8 as indicated in the figure showing the component symbol. The power module offers two configurations:

Switched

All power semiconductors inside the module are modeled with ideal switches. The individual switches are controlled with logical gate signals. A switch is on if the corresponding gate signal is not zero. For compatibility with the averaged configuration it is recommended to use the value \(1\) for non-zero gate signals.

Sub-cycle average

The module as a whole is modeled with controlled voltage and current sources. The DC side of the inverter bridge has current source behavior and must be connected to positively biased capacitors or voltage sources. The AC side is typically connected to an inductor. The control inputs are the relative on-times of the switches with values between \(0\) and \(1\).

In the average configuration the half bridge can be operated in two ways:

  • The control signals are instantaneous logical gate signals having the values \(0\) and \(1\).

  • The control signals are the duty cycles of the individual switches. They are either computed directly from the modulation index or by periodically averaging the digital gate signals over a fixed period of time, e.g. using the Periodic Average block. The averaging period does not need to be synchronized with the PWM and can be as large as the inverse of the switching frequency.

In both use cases, the average implementation correctly accounts for blanking times, i.e. when during commutation less than two switches are turned on. It also supports discontinuous conduction mode, e.g. when charging the DC link capacitors via the reverse diodes.

Since the duty cycle is simulated accurately even with relatively large time steps, the average configuration is particularly well suited for real-time simulations with high switching frequencies.

The sub-cycle average model implementation requires an internal switching element on the AC side. When generating code for the power module the switching element is modeled as either an ideal or non-ideal switch. See Ideal and Non-Ideal Switch Models in Electric Circuits for detailed descriptions of the switch model implementations.

Note

The sub-cycle average implementation cannot model a shoot-through or clamping of the DC side. Therefore, the sums of the control signals for switches must respect the given restrictions summarized below under the Assertions parameter at any time. Also, the applied DC voltages must never become negative.

Parameters

Configuration

Switched or averaged circuit model.

Semiconductor symbol

This setting lets you choose between IGBT and MOSFET for the symbol the active semiconductor switches. This setting does not change the electrical behavior of the power module in simulation.

Assertions

When set to on, the block will flag an error if the sums of the control signals for:

  • S1 and S2

  • S3 and S4

  • S5 and S8

  • S6 and S7

become larger than \(1\) at any point in time.

Switch model (CPU code generation)

Select the switch model in the generated code.