PLL (Three-Phase)

Purpose

Implementation of a three-phase PLL

Library

Control / Continuous

Description

This block implements two different types of a three-phase Phase Locked Loop (PLL). The PLL block provides an estimation of the phase-angle, amplitude and frequency of the three-phase input signal.

PLL Types

General PLL Structure

The general PLL structure shown of a three-phase PLL can be divided into three basic blocks:

• Phase detector: Generates an output signal that is proportional to the phase difference between the input signal and the signal generated by the PLL itself.

• Controller: Usually a PI controller to attenuate high-frequency components and to eliminate the steady-state phase-error.

• Frequency/phase-angle generator: Generates a phase-angle signal based on the estimated angular frequency. Typically, this block is constituted by a wrapping integrator.

Fig. 155 General PLL block diagram

The main difference between the two offered three-phase PLLs lies in the phase detector part.

SRF-PLL

A basic synchronization technique in three-phase applications is the synchronously rotating reference frame PLL (SRF-PLL). The three-phase voltage vector in the natural reference frame is transformed in the rotating reference frame by using the Park transformation. The instantaneous phase angle is controlled by a feedback loop that regulates the q component to zero. Under steady-state operation, i.e. when the q component is zero, the d component depicts the amplitude of the input voltage vector. This simple approach works fine if the grid voltage is not affected by harmonics or unbalances. To avoid the impact of voltage harmonics on the accuracy of the estimated phase-angle and frequency, the controller bandwidth has to be set as high as possible. However, under unbalanced grid conditions, a double-frequency ripple of the input signal frequency is visible on the output signals of the PLL if the control-loop bandwidth is set to high. Therefore, a trade-off between those two control goals has to be made.

Fig. 156 Phase detector of the SRF-PLL

DSRF-PLL

The decoupled double synchronous reference frame PLL uses two synchronous reference frames, rotating with positive and negative synchronous speeds, respectively. This allows the decoupling of the effect of the negative sequence component on the dq-signals. This is of high interest when synchronizing to non-ideal grids, i.e unbalanced voltage conditions. Since the double-frequency ripple caused by the unbalanced grid condition is avoided, a higher control bandwidth compared to the SRF-PLL can be set.

Fig. 157 Phase detector of the DSRF-PLL

The transfer function of the low-pass filter in Fig. 157 can be written as:

\[\frac{V_{out}(s)}{V_{in}(s)} = \frac{k \omega_0}{s + k \omega_0}\]

By decreasing the filter gain \(k\), the bandwidth of the LPF can be reduced accordingly.

Parameters

Basic

PLL type

Specifies the PLL type. The three-phase PLL can be of type SRF-PLL or DSRF-PLL. For further explanations on the different PLL implementations see PLL types above.

Nominal frequency

The nominal frequency of the fundamental component in hertz or radians/second, see below.

Nominal input voltage

The estimated nominal peak voltage of the input signal in volts \((\mathrm{V})\). This value is needed to correctly initialize all states in the PLL structure. If this information is not known, this parameter can be set to zero.

Initial phase-angle

The initial phase-angle of the input signal in rad, per unit \((\mathrm{p.u.})`\) or degrees, see below. The parameter value should be in the range \([0, 2\pi]\), \([0, 1]\) or \([0, 360]\) respectively.

Units for frequency and phase

The frequency and phase can be expressed in terms of (rad/s, rad), (Hz, p.u.) or (Hz, degrees). If the phase is expressed in per unit \((\mathrm{p.u.})\), a value of 1 is equivalent to the period length of the nominal frequency. This parameter also changes the unit of the frequency output of the PLL component.

Controller design

Controller design

Specifies the controller design approach. If the parameter is set to Basic, the PI controller gains are automatically set. If the PLL type parameter is set to SRF-PLL, the PLL is designed to have a controller crossover frequency of half the nominal frequency defined in the parameter Nominal frequency and a phase margin of at least \(60^{\circ}\). Otherwise, if the PLL type parameter is set to DSRF-PLL, the PLL is designed to have a controller crossover frequency equal to the nominal frequency defined in the parameter Nominal frequency and a phase margin of at least \(60^{\circ}\). By using the Advanced approach, the user can specify the controller Kp and Ki and the filter gain k freely. Please note, the controller gains have not to be scaled by the rated input signal amplitude since the both schemes use an amplitude normalization scheme.

Proportional gain Kp

The proportional gain of the PI controller. This parameter is shown only if the Controller design parameter is set to Advanced.

Integral gain Ki

The integral gain of the PI controller. This parameter is shown only if the Controller design parameter is set to Advanced.

Filter coefficient k

The filter gain of the PI controller. This parameter is shown only if the Controller design parameter is set to Advanced and the PLL type parameter is set to DSRF-PLL.

Probe Signals

Theta

The estimated phase-angle of the input signal.

Amplitude

The estimated amplitude of the input signal.

Frequency

The estimated frequency of the input signal.

Input Signal

The input signal of the three-phase PLL block.

References

• R. Teodorescu, et. al., “Grid Converters for Photovoltaic and Wind Power Systems”, John Wiley & Sons Ltd., 2011.