(M) MOSFET Statement

PLECS Spice supports a modified version of the standard Level 1 and Level 3 MOSFET model as well as a model for a vertically-diffused MOSFET (VDMOS).

Classic SPICE MOSFET models

The static equations for the supported LEVEL=1 and LEVEL=3 MOSFET models are identical to a larger extent to those of the original Spice3f5 models. We have made minor modeling improvements to make the equations continuous, notably for the bulk junctions and for the evaluation of the threshold voltage. Regarding the large-signal model, we do not support the Meyer model of the intrinsic charges because it does not conserve charge. Instead, a simplified version of the BSIM3v3.3 charge model is implemented (capMod=2, 0/100 charge partition).

Mname drain gate source bulk modelName <<L>=l> <<W>=w> <AD=ad> <AS=as> <PD=pd> <PS=ps> <NRD=nrd> <NRS=nrs> <IC=vds,vgs,vbs> <TEMP=temp> <M=m>
.MODEL modelName NMOS <NAME=value ...>
Mname drain gate source <bulk> modelName <<L>=l> <<W>=w> <AD=ad> <AS=as> <PD=pd> <PS=ps> <NRD=nrd> <NRS=nrs> <off> <IC=vds,vgs,vbs> <TEMP=temp> <M=m>
.MODEL modelName NMOS <NAME=value ...>
  • When bulk is omitted, it is assumed that bulk is the same as source.

  • During the operating point analysis, an initial guess for (\(V_\text{ds}\), \(V_\text{gs}\), \(V_\text{bs}\)) is chosen such that the MOSFET starts at the onset of conduction. When the off flag is set, the initial voltage guesses are set to zero instead. Note that this option does not enforce a constraint on the solution found during the operating point analysis.

  • The MOSFET device type NMOS or PMOS must be specified in the model statement.

  • You can customize this model by providing a list of model parameter (name-value format) at the end of the .MODEL statement.

  • When importing a MOSFET model, the bulk node will be set equal to the source node

Instance Parameters

Parameter

Description

Default Value

L

Channel length

\(10^{-4}\,\text{m}\)

W

Channel width

\(10^{-4}\,\text{m}\)

AD

Drain diffusion area

\(0\,\text{m}^2\)

AS

Source diffusion area

\(0\,\text{m}^2\)

PD

Drain diffusion perimeter

\(0\,\text{m}\)

PS

Source diffusion perimeter

\(0\,\text{m}\)

NRD

Number of drain squares

\(1\)

NRS

Number of source squares

\(1\)

IC

Initial condition voltages (\(V_{\text{ds}}, V_{\text{gs}}, V_{\text{bs}}\)).

none

TEMP

Device temperature

\(27\,^\circ\text{C}\)

M

Number of parallel devices

\(1\)

  • When the IC parameter is given, initial values for the drain-source (\(V_{\text{ds}}\)), the gate-source (\(V_{\text{gs}}\)), and bulk-source voltage (\(V_{\text{bs}}\)) must be specified.

Model Parameters

Parameter

Description

Default Value

T_ABS

Device temperature

\(27\,^\circ\text{C}\)

TNOM

Nominal temperature

\(27\,^\circ\text{C}\)

LEVEL

Specifies the level of the MOSFET model

\(1\)

VTO / VT0

Zero-bias threshold voltage

\(0\,\text{V}\)

PHI

Surface-inversion potential

\(0.6\,\text{V}\)

KP

Transconductance

\(2\times 10^{-5}\,\text{A}/\text{V}^2\)

GAMMA

Bulk threshold parameter

\(0\,\text{V}^{0.5}\)

UO / U0

Surface mobility

\(600\,\text{cm}^2/(\text{V}\text{s})\)

NSS

Surface state density

\(0\,\text{cm}^{-2}\)

NSUB

Substrate doping

\(0\,\text{cm}^{-3}\)

TPG

Type of the gate material

\(1\)

LD

Lateral diffusion length

\(0\,\text{m}\)

TOX

Gate insulation oxide thickness

\(10^{-7}\,\text{m}\)

CGSO

Gate-source overlap capacitance per channel width

\(0\,\text{F}/\text{m}\)

CGDO

Gate-drain overlap capacitance per channel width

\(0\,\text{F}/\text{m}\)

CGBO

Gate-bulk overlap capacitance per channel length

\(0\,\text{F}/\text{m}\)

IS

Reverse saturation current for the bulk-drain and bulk-source junctions

\(10^{-14}\,\text{A}\)

JS

Reverse saturation current density for the bulk-drain and bulk-source junctions

\(0\,\text{A}/\text{m}^2\)

XTI

Temperature exponent for IS and JS

\(1\)

N

Emission coefficient for the bulk-drain and bulk-source junctions

\(1\)

PB

Junction potential for the bulk-drain and bulk-source junctions

\(0.75\,\text{V}\)

MJ

Grading coefficient for the bulk-drain and bulk-source junctions

\(0.5\)

CBD

Bulk-drain zero-bias junction capacitance

\(0\,\text{F}\)

CBS

Bulk-source zero-bias junction capacitance

\(0\,\text{F}\)

CJ

Zero-bias junction capacitance per unit area

\(0\,\text{F}/\text{m}^2\)

MJSW

Grading coefficient for the sidewall junction capacitance

0.5 (LEVEL=1) 0.33 (LEVEL=3)

CJSW

Zero-bias sidewall junction capacitance

\(0\,\text{F}/\text{m}\)

FC

Forward-bias depletion capacitance coefficient

\(0.5\)

TT

Forward transit time for the bulk-drain and bulk-source junctions

\(0\,\text{s}\)

RSH

Channel sheet resistance

\(0\,\Omega\)

RD

Drain resistance

NRD x RSH

RS

Source resistance

NRS x RSH

RG

Gate resistance

\(0\,\Omega\)

RB

Bulk resistance

\(0\,\Omega\)

RDS

Drain-source resistance

\(+\infty\,\Omega\)

  • When TPG it set to 1 (-1), it is assumed that the gate material has opposite (same) doping than the substrate. For an aluminum gate, set TPG to zero.

  • You can specify the instance parameters L, W, AD, AS, PD, PS, NRD, and NRS as model parameters too. If both are provided, the instance values take priority.

  • The instance parameter TEMP overwrites the model parameter T_ABS.

Additional Parameters for the LEVEL=1 model

Parameter

Description

Default Value

LAMBDA

Channel length modulation

\(0\,\text{V}^{-1}\)

Additional Parameters for the LEVEL=3 model

Parameter

Description

Default Value

DELTA

Width effect on threshold voltage

\(0\)

ETA

Static feedback on the threshold voltage

\(1\)

KAPPA

Saturation field factor

\(0.2\)

NFS

Fast surface state density

\(0\,\text{cm}^{-2}\)

THETA

Mobility modulation

\(0\,\text{V}^{-1}\)

VMAX

Maximum carrier drift velocity

\(+\infty\,\text{m}/\text{s}\)

XJ

Metallurgical junction depth

\(0\,\text{m}\)

Note

We assume a different default value for VMAX than the original SPICE solvers. You can set VMAX=0 to reproduce the standard SPICE behavior.

VDMOS model

A simple model for a VDMOS, based on the static LEVEL=1 MOSFET equations and an explicitly modeled body diode, is supported. While the gate-source capacitance is assumed constant, the gate-drain capacitance is modelled empirically using a nonlinear equation.

Mname drain gate source modelName <IC=vds,vgs> <TEMP=temp> <M=m>
.MODEL modelName VDMOS <nchan> <NAME=value ...>
Mname drain gate source source modelName <off> <IC=vds,vgs> <TEMP=temp> <M=m>
.MODEL modelName VDMOS <nchan> <NAME=value ...>
  • During the operating point analysis, an initial guess for (\(V_\text{ds}\), \(V_\text{gs}\)) is chosen such that the VDMOS starts at the onset of conduction. When the off flag is set, the initial voltage guesses are set to zero instead. Note that this option does not enforce a constraint on the solution found during the operating point analysis.

  • If a fourth terminal is given, it must coincide with the third terminal.

  • The VDMOS device type VDMOS must be specified in the model statement. The polarity of the device is set with the nchan (default) or the pchan flag.

  • You can customize this model by providing a list of model parameter (name-value format) at the end of the .MODEL statement.

Instance Parameters

Parameter

Description

Default Value

IC

Initial condition voltages (\(V_{\text{ds}}, V_{\text{gs}}\)).

none

TEMP

Device temperature

\(27\,^\circ\text{C}\)

M

Number of parallel devices

\(1\)

  • When the IC parameter is given, initial values for both the drain-source (\(V_{\text{ds}}\)), and the gate-source (\(V_{\text{gs}}\)) voltage must be specified.

Model Parameters

Parameter

Description

Default Value

TNOM

Nominal temperature

\(27\,^\circ\text{C}\)

VTO

Zero-bias threshold voltage

\(0\,\text{V}\)

KP

Transconductance

\(1\,\text{A}/\text{V}^2\)

LAMBDA

Channel length modulation

\(0\,\text{V}^{-1}\)

MTRIODE

Conductance multiplier in the linear regime

\(1\)

SUBSHIFT

Shift in gate-source voltage of the subthreshold model

\(0\,\text{V}\)

KSUBTHRES

Subthreshold parameter

\(0.1\,\text{V}\)

CGDMAX

Maximum value of the gate-drain capacitance

\(0\,\text{F}\)

CGDMIN

Minimum value of the gate-drain capacitance

\(0\,\text{F}\)

A

Gate-drain capacitance parameter

\(1\)

CGS

Gate-source capacitance

\(0\,\text{F}\)

RD

Drain resistance

\(0\,\Omega\)

RS

Source resistance

\(0\,\Omega\)

RG

Gate resistance

\(0\,\Omega\)

RDS

Drain-source resistance

\(+\infty\,\Omega\)

IS

Reverse saturation current (body diode)

\(10^{-14}\,\text{A}\)

XTI

Temperature exponent for IS (body diode)

\(3\)

EG

Band gap energy (body diode)

\(1.11\,\text{eV}\)

N

Emission coefficient (body diode)

\(1\)

BV

Reverse breakdown voltage (body diode)

\(\infty\,\text{V}\)

IBV

Reverse breakdown current (body diode)

\(10^{-10}\,\text{A}\)

NBV

Emission coefficient for the reverse breakdown current (body diode)

\(1\)

VJ

Junction potential (body diode)

\(0.8\, \text{V}\)

M

Junction grading coefficient (body diode)

\(0.5\)

CJO

Zero-bias junction capacitance (body diode)

\(0\,\text{F}\)

FC

Forward-bias depletion capacitance coefficient (body diode)

\(0.5\)

TT

Forward transit time (body diode)

\(0\,\text{s}\)

RB

Series resistance (body diode)

\(0\,\Omega\)

Note

  • Some parameters encountered in semiconductor models are provided as additional information and do not affect the simulation. PLECS Spice ignores the following parameters: mfg, Vds, Ron, Qg.

Examples

M1 d g s s nmosModel TEMP=125
.MODEL nmosModel NMOS LEVEL=1 VTO=3.5 KP=100 RD=0.05 RS=0.02 CGSO=1n CGDO=500p