Three-level Grid-connected NPC Solar Inverter with LCL-filter and Active Damping

Overview

This RT Box demo model features a grid-connected three-level neutral-point clamped (NPC) inverter with closed-loop control using a space-vector pulse-width modulation (SVPWM) scheme. This demo model has the following features:

• The plant and controller models are implemented inside one subsystem. This allows a complete transient offline simulation in PLECS, as well as a real-time simulation of both controller and plant model.

• The inverter delivers \(50\,\mathrm{kW}\) from an \(800\,\mathrm{V}\) DC input to a \(50\,\mathrm{Hz}\), \(230\,\mathrm{V_{rms}}\) stiff grid. The link between the inverter and the stiff grid features an LCL-filter. The resonance brought by the LCL-filter may lead to controller instability, thus some damping technique is needed to suppress this resonance peak. In this demo model, an active damping technique is employed over passive damping, with the merit of less power losses.

This document describes the implementation of the power stage and controls using the PLECS Electrical and Control domains. It presents the current control and modulation with a special focus on the three-level SVPWM technique, and the necessary neutral-point balancing algorithm is also included.

The execution time represents the actual time it takes to execute one calculation step of the PLECS model on the RT Box hardware. The chosen discretization step sizes and average execution times for each core on the RT Box are shown in Tab. 1.

Table 1 Discretization step size and average execution time of the demo on one RT Box

	Core 0: exec. time / step size	Core 1: exec. time / step size	FlexArray step size
RT Box 2, 3 or 4	\(2.5\,\mu\mathrm{s}\) / \(5\,\mu\mathrm{s}\)	\(1.8\,\mu\mathrm{s}\) / \(50\,\mu\mathrm{s}\)	\(250\,n\mathrm{s}\)
RT Box 1	\(8.5\,\mu\mathrm{s}\) / \(10\,\mu\mathrm{s}\)	N/A	N/A

Requirements

To run this demo model, the following items are needed (available at www.plexim.com):

• One PLECS RT Box and one PLECS Coder license

• The RT Box Target Support Package

• Follow the step-by-step instructions on configuring PLECS and the RT Box in the Quick Start guide of the RT Box Target Support Package Documentation.

• Two 37 pin Sub-D cables to connect the box in loop-back setup at the front panel.

Note that this demo model primarily showcases the RT Box multi-tasking mode. All RT Boxes support multi-tasking, but the implementation differs depending on the model.

Note

The RT Box CE cannot be used for this demo due to its reduced amount of analog input channels.

• When the target is an RT Box 2, 3 or 4, the main CPU core (Core 0) runs the plant as “Base task” with a sample time of Ts_plant. Another core (Core 1) runs closed-loop controls in “Controller” task in parallel with a sample time of Ts_controller, which is much slower and usually equals the switching period of the converter. In this way, the multi-core feature of the RT Box 2, 3 or 4 is showcased by splitting the computational effort onto different cores. Besides, the setup can easily transition to a HIL or RCP test later on.

• However if the user has only a single RT Box 1 available, this model can also run with the multi-tasking feature onto the only CPU core of the RT Box 1, but in a pre-emptive multi-tasking fashion. In this case, the “Base task” is doing the plant calculation with the highest priority with a sample time of Ts_plant. The “Controller” task is executed as a background task with lower priority at the sample time of Ts_controller.

Please check the setting under Scheduling tab of the Coder options… window.

Note

This model contains model initialization commands that are accessible from:

PLECS Standalone: the menu Simulation > Simulation Parameters… > Initializations

PLECS Blockset: right click in the Simulink model window > Model Properties > Callbacks > InitFcn*

Model

The top-level schematic of the demo model is depicted in Fig. 1, and it is composed of one subsystem: “Plant + Controller”. To run the model on an RT Box, the subsystem has to be configured as atomic units and enabled for code generation by right-clicking on the subsystem and choosing Subsystem + Execution settings…

A Delay block (\(\textrm{z}^{-1}\)) with a sample time equal to one controller task step is added to the offline simulation before the analog input of the controller subsystem. This emulates the calculation time delay of one control step in the real-time application.

Fig. 1 Top-level schematic of the three-level NPC inverter model

Three-Level NPC Inverter with LCL-Filter and Active Damping

Fig. 2 shows the circuit model of the plant, which comprises a three-level NPC inverter connected to the grid through an LCL-filter.

Fig. 2 Schematic of the grid-connected three-level NPC inverter with LCL-filter and active damping

• DC input: The DC input is modeled with a simplified photovoltaic (PV) panel model. The block input is the relative solar intensity level (nominal value of 1) set by the Constant block “Sun”. The PV panel output is the intensity level multiplied with a fixed DC voltage of \(800\,\mathrm{V}\).

• Upper and lower half DC capacitors: The upper and lower half DC capacitors have the same \(1.1\,\mathrm{mF}\) capacitance value, however, in order to see the effect of the neutral-point balancing algorithm, different initial voltage values are set. Later in the real-time simulation result in section Simulation, one can see that the upper and lower half DC capacitors, with initial voltages of \(450\,\mathrm{V}\) and \(350\,\mathrm{V}\), respectively, settle at a balanced \(400\,\mathrm{V}\) and \(400\,\mathrm{V}\). The neutral-point balancing algorithm is further discussed in section Three-Level Space-Vector Pulse-Width Modulation Scheme and Controls.

• Three-level NPC inverter: The IGBT 3-Level Half Bridge power modules from the PLECS component library are used to build up the NPC inverter topology. The modules use the sub-cycle average configuration together with the PWM Capture blocks. This ensures that incoming switching signals are sampled with high resolution, and subsequently physical states are properly calculated. This configuration is able to run online in real-time, as well as offline with a variable-step solver.

The plant model uses different blocks from the RT Box Target Support Library to access the physical input and output ports of the RT Box: the PWM Capture and Analog Output blocks, respectively. A generic description of these blocks is given in the RT Box Target Support Package Documentation or the “Boost Converter” RT Box demo model.

LCL-filter design

Due to the pulsating voltage at the three-level inverter output nodes, some kind of filter has to be inserted between the inverter and the grid to attenuate the switching harmonics. The filter is usually composed of inductors and capacitors, which allow the inverter to exchange active and reactive power with the grid by means of inverter control. The design guideline of the LCL-filter used here follows reference [1].

Filter capacitor \(C_{\mathrm{f}}\) design

To design \(C_{\mathrm{f}}\) we have to consider reactive power variations due to the LCL-filter. The design base values can be defined as:

\[{Z}_{\mathrm{b}}=\frac{V^2_{\mathrm{LL}}}{P_{\mathrm{n}}}, {C}_{\mathrm{b}}=\frac{1}{\omega_{\mathrm{g}}Z_{\mathrm{b}}}, {L}_{\mathrm{b}}=\frac{Z_{\mathrm{b}}}{\omega_{\mathrm{g}}},\]

where \(V^2_{\mathrm{LL}}\) is grid line-to-line RMS voltage, \(P_{\mathrm{n}}\) is the rated active power, and \(\omega_{\mathrm{g}}=2\pi{f}_{\mathrm{g}}\) is the grid angular frequency. Filter capacitance is related to the base value \(C_{\mathrm{b}}\) as a percentage of it. Setting the maximum power variation seen by the grid as 5% (empirical value 1% - 5%), we can obtain:

\[{C}_{\mathrm{f}}=0.05{C}_{\mathrm{b}}\]

Filter inductors \(L_{\mathrm{c}}\) and \(L_{\mathrm{g}}\) design

At low frequencies the LCL-filter behaves like an inductor with the total inductance of:

\[{L}_{\mathrm{dc}}={L}_{\mathrm{c}}+{L}_{\mathrm{g}}\]

Note that the current through filter capacitors \(C_{\mathrm{f}}\) is negligible compared to that of the filter inductors. There is a relation between \({L}_{\mathrm{c}}\) and \({L}_{\mathrm{g}}\) that minimizes the voltage drop at the fundamental frequency and maximizes filtering ability. If we express \({L}_{\mathrm{c}}\) and \({L}_{\mathrm{g}}\) as a percentage of \({L}_{\mathrm{dc}}\) with \(\alpha\) \(\in\) [0, 1], then:

\[{L}_{\mathrm{c}}=\alpha{L}_{\mathrm{dc}}, {L}_{\mathrm{g}}=(1-\alpha){L}_{\mathrm{dc}}\]

Since the LCL resonant circuit consists of \({L}_{\mathrm{c}}\), \({C}_{\mathrm{f}}\), and \({L}_{\mathrm{g}}\) all in parallel, the LCL resonant frequency is:

\[\omega_{\mathrm{r}} = \sqrt{\frac{L_{\mathrm{c}} + L_{\mathrm{g}}}{L_{\mathrm{c}} C_{\mathrm{f}} L_{\mathrm{g}}}}\]

Therefore the equivalent inductance \({L}_{\mathrm{eq}}\) that sets the resonant frequency can be defined as \({L}_{\mathrm{c}}\) and \({L}_{\mathrm{g}}\) in parallel:

\[{L}_{\mathrm{eq}}=\frac{{L}_{\mathrm{c}}{L}_{\mathrm{g}}}{{L}_{\mathrm{c}}+{L}_{\mathrm{g}}}=\alpha(1-\alpha){L}_{\mathrm{dc}}\]

The minimum \({L}_{\mathrm{eq}}\) is achieved when \({L}_{\mathrm{c}}={L}_{\mathrm{g}}=0.5{L}_{\mathrm{dc}}\). By choosing \({L}_{\mathrm{dc}}\) to be 10% (empirical value) of the base value \(L_{\mathrm{b}}\), \({L}_{\mathrm{c}}\) and \({L}_{\mathrm{g}}\) are easily determined:

\[{L}_{\mathrm{c}}={L}_{\mathrm{g}}=0.05 {{L}_{\mathrm{b}}}\]

Active damping technique using filter capacitor currents

To suppress the high peak gain at the LCL resonant frequency, a damping resistor for the input filter can be placed as a passive damping method [2]. Passive damping is a simple approach but introduces additional losses, while active damping solves the problem through a control modification with a virtual resistor which is lossless.

Fig. 3 depicts the single-phase equivalent ideal LCL-filter and its corresponding block diagram [1]. Fig. 4 demonstrates the case of a damped filter, where the damping resistor is placed in series with the filter capacitor [1]. The block diagram in Fig. 4 shows that with a virtual gain component (emulating “RD” in Fig. 4) the same damping effect can be added to the control scheme of an ideal LCL-filter while removing the power losses of the physical damping resistor. For the active damping approach, filter capacitor currents have to be measured, which requires three (or only two for the case of balanced three-phase currents) additional analog in-/outputs.

Fig. 3 Single-phase equivalent ideal LCL-filter and corresponding block diagram

Fig. 4 Single-phase equivalent damped LCL-filter and model, damping resistor in series with capacitor

The filter in Fig. 3 can be described with the state equations in the \(s\)-domain:

\[{v}_{\mathrm{c}}(s) = s{L}_{\mathrm{c}}{i}_{\mathrm{c}}(s) + {v}_{\mathrm{f}}(s)\]

\[{v}_{\mathrm{g}}(s) = {v}_{\mathrm{f}}(s) - s{L}_{\mathrm{g}}{i}_{\mathrm{g}}(s)\]

\[{v}_{\mathrm{f}}(s) = \frac{{i}_{\mathrm{f}}(s)}{s{C}_{\mathrm{f}}}\]

\[{i}_{\mathrm{c}}(s) = {i}_{\mathrm{f}}(s) + {i}_{\mathrm{g}}(s)\]

The voltage and current transfer functions of the ideal LCL-filter are therefore:

\[{H}_{\mathrm{{v}}_{\mathrm{f}}}(s) = \frac{{v}_{\mathrm{f}}(s)}{{v}_{\mathrm{c}}(s)} = \frac{1}{{L}_{\mathrm{c}}{C}_{\mathrm{f}}} \frac{1}{s^2 + \omega_{\mathrm{r}}^2}\]

\[{H}_{\mathrm{{i}}_{\mathrm{f}}}(s) = \frac{{i}_{\mathrm{f}}(s)}{{v}_{\mathrm{c}}(s)} = \frac{{i}_{\mathrm{f}}(s)}{{v}_{\mathrm{f}}(s)} \frac{{v}_{\mathrm{f}}(s)}{{v}_{\mathrm{c}}(s)} = \frac{1}{{L}_{\mathrm{c}}} \frac{s}{s^2 + \omega_{\mathrm{r}}^2}\]

where \(\omega_{\mathrm{r}}\) is the resonant frequency defined before.

For the LCL-filter with damping resistance in Fig. 4 we have:

\[{v}_{\mathrm{c}}^d(s) = s\cdot{L}_{\mathrm{c}}\cdot{i}_{\mathrm{c}}^d(s) + {v}_{\mathrm{f}}^d(s)\]

\[{v}_{\mathrm{g}}^d(s) = {v}_{\mathrm{f}}^d(s) - s\cdot{L}_{\mathrm{g}}\cdot{i}_{\mathrm{g}}^d (s)\]

\[{v}_{\mathrm{f}}^d(s) = {i}_{\mathrm{f}}^d(s)\left(R_{\mathrm{D }} + \frac{1}{s{C}_{\mathrm{f}}}\right)\]

\[{i}_{\mathrm{c}}^d(s) = {i}_{\mathrm{f}}^d(s) + {i}_{\mathrm{g}}^d(s)\]

The damping resistor \(R_{\mathrm{D}}\) is often selected as one third of the impedance of the filter capacitor \(C_{\mathrm{f}}\) at resonant frequency [1]:

\[R_{\mathrm{D}} = \frac{1}{3 \omega_{\mathrm{r}}C_{\mathrm{f}}}\]

Therefore we can derive the same voltage and current transfer functions of interest:

\[{H}^d_{\mathrm{{v}}_{\mathrm{f}}}(s) = \frac{{v}^d_{\mathrm{f}}(s)}{{v}^d_{\mathrm{c}}(s)} = \frac{1}{{L}_{\mathrm{c}}{C}_{\mathrm{f}}} \frac{1+sR_{\mathrm{D}}C_{\mathrm{f}}}{s^2 + \omega^2_{\mathrm{r}}(1+sR_{\mathrm{D}}C_{\mathrm{f}})}\]

\[{H}^d_{\mathrm{{i}}_{\mathrm{f}}}(s) = \frac{{i}^d_{\mathrm{f}}(s)}{{v}^d_{\mathrm{c}}(s)} = \frac{{i}^d_{\mathrm{f}}(s)}{{v}^d_{\mathrm{f}}(s)} \frac{{v}^d_{\mathrm{f}}(s)}{{v}^d_{\mathrm{c}}(s)}= \frac{1}{{L}_{\mathrm{c}}} \frac{s}{s^2 + \omega_{\mathrm{r}}^2(1+sR_{\mathrm{D}}C_{\mathrm{f}})}\]

For the case without damping resistance, we define:

\[{H}_{\mathrm{{v}}_{\mathrm{f}}}(s) = \frac{{v}_{\mathrm{f}}(s)}{{v}_{\mathrm{c}}(s)} = \frac{L_{\mathrm{g}}}{s^2{L}_{\mathrm{c}}{C}_{\mathrm{f}}L_{\mathrm{g}} + L_{\mathrm{c}} + L_{\mathrm{g}}} = H_{\mathrm{1}}(s)\]

\[\frac{{i}_{\mathrm{f}}(s)}{{v}_{\mathrm{f}}(s)} = s{C}_{\mathrm{f}} = H_{\mathrm{2}}(s)\]

For the case with damping resistance, we define:

\[{H}^d_{\mathrm{{v}}_{\mathrm{f}}}(s) = \frac{{v}^d_{\mathrm{f}}(s)}{{v}^d_{\mathrm{c}}(s)} = \frac{L_{\mathrm{g}}(1+sR_{\mathrm{D}}C_{\mathrm{f}})}{s^2{L}_{\mathrm{c}}{C}_{\mathrm{f}}L_{\mathrm{g}} + (L_{\mathrm{c}} + L_{\mathrm{g}})(1+sR_{\mathrm{D}}C_{\mathrm{f}})} = H_{\mathrm{3}}(s)\]

For the active damping technique, we would like to achieve \(H_{\mathrm{3}}(s)\) without a physical \(R_{\mathrm{D}}\), but rather with a virtual resistor with the value of \(R_{\mathrm{D}}\). Fig. 5 shows the block diagram of the active damping control loop with the gain of \(K_{\mathrm{AD}}\). We want the closed-loop transfer function in Fig. 5 to be similar to \(H_{\mathrm{3}}(s)\).

Fig. 5 Active damping control loop block diagram with capacitor voltage/current as feedback

Thus in Fig. 5,

\[\begin{split}\begin{aligned} {H}_{\mathrm{CL}}(s) ={}& \frac{H_{\mathrm{1}}(s)}{1 + H_{\mathrm{1}}(s)H_{\mathrm{2}}(s)K_{\mathrm{AD}}} = \frac{\frac{L_{\mathrm{g}}}{s^2{L}_{\mathrm{c}}{C}_{\mathrm{f}}L_{\mathrm{g}} + L_{\mathrm{c}} + L_{\mathrm{g}}}}{1 + \frac{L_{\mathrm{g}}}{s^2{L}_{\mathrm{c}}{C}_{\mathrm{f}}L_{\mathrm{g}} + L_{\mathrm{c}} + L_{\mathrm{g}}} s C_{\mathrm{f}} K_{\mathrm{AD}}} \\ {}={}& \frac{L_{\mathrm{g}}}{s^2{L}_{\mathrm{c}}{C}_{\mathrm{f}}L_{\mathrm{g}} + L_{\mathrm{c}} + L_{\mathrm{g}} + s L_{\mathrm{g}} C_{\mathrm{f}} K_{\mathrm{AD}}} \end{aligned}\end{split}\]

And with \(K_{\mathrm{AD}}\) selected as:

\[K_{\mathrm{AD}} = \frac{L_{\mathrm{c}} + L_{\mathrm{g}}}{L_{\mathrm{g}}} R_{\mathrm{D}}\]

we have

\[{H}_{\mathrm{CL}}(s) = \frac{L_{\mathrm{g}}}{s^2{L}_{\mathrm{c}}{C}_{\mathrm{f}}L_{\mathrm{g}} + L_{\mathrm{c}} + L_{\mathrm{g}} + s L_{\mathrm{g}} C_{\mathrm{f}} \frac{L_{\mathrm{c}} + L_{\mathrm{g}}}{L_{\mathrm{g}}} R_{\mathrm{D}}} = \frac{L_{\mathrm{g}}}{s^2{L}_{\mathrm{c}}{C}_{\mathrm{f}}L_{\mathrm{g}} + (L_{\mathrm{c}} + L_{\mathrm{g}})(1+sR_{\mathrm{D}}C_{\mathrm{f}})}\]

This final \({H}_{\mathrm{CL}}(s)\) is close enough to \(H_{\mathrm{3}}(s)\) that we can neglect the term “\(R_{\mathrm{D}} C_{\mathrm{f}}\)” in the numerator of \(H_{\mathrm{3}}(s)\) since it is much smaller than 1. Note that the implementation should be considered for both axis regulator for \(i_{\mathrm{d}}\) and \(i_{\mathrm{q}}\). This virtual damping gain \(K_{\mathrm{AD}}\) is located inside the controller subsystem (see later Fig. 6) as the Gain block “Virtual damping resistor”.

Three-Level Space-Vector Pulse-Width Modulation Scheme and Controls

The controller subsystem including measurement transformation, three-level SVPWM and closed-loop dq current controller are captured in Fig. 6. It contains Analog In and PWM Out blocks from the RT Box Target Support library. A generic description of these blocks is given in the RT Box Target Support Package Documentation or the “Boost Converter” RT Box demo model.

The \(i_{\mathrm{d}}\) and \(i_{\mathrm{q}}\) current controllers are designed using the Magnitude Optimum Criterion based on the following transfer function:

\[{H}_{\mathrm{OL}}(s) \approx \frac{1}{R_{\mathrm{g}}+R_{\mathrm{c}}+(L_{\mathrm{g}}+L_{\mathrm{c}})s}\]

This neglects the small current flowing into the filter capacitors and the stiff grid inductance \(L_{\mathrm{grid}}\ll L_{\mathrm{g}}\).

Fig. 6 Control scheme of the grid-connected three-level NPC inverter using SVPWM method

SVPWM Scheme

There are three NPC legs (phases u, v, and w) shown in Fig. 2. Each leg contains four switches Qx1, Qx2, Qx3, and Qx4 (x = u, v, and w), and these four switches must be controlled in two complementary pairs. Qx1 and Qx3 make one complementary pair, while Qx2 and Qx4 make the other pair. By controlling these four switches the inverter output allows for three different voltage levels. Tab. 2 lists the three valid states for each leg, in which P means a switch leg is connected to the positive DC rail, N means it is connected to the negative DC rail, and O means it is connected to the neutral-point potential.

Table 2 Output status of each leg based on different switching combination of Qx1-Qx4

Switch No.	Qx1	Qx2	Qx3	Qx4	Phase voltage	Leg status
1	ON	ON	OFF	OFF	\(\frac{V_{\mathrm{dc}}}{2}\)	P
2	OFF	OFF	ON	ON	-\(\frac{V_{\mathrm{dc}}}{2}\)	N
3	OFF	ON	ON	OFF	0	O

Thus, in total there are 27 states of the three-level VSI which can be mapped to the space-vector diagram, depicted in Fig. 7. Assuming a reference vector \(V_{\mathrm{ref}}\), according to the theory of SVPWM, we need to find the two nearest vectors \(V_{\mathrm{X}}\), \(V_{\mathrm{Y}}\) and one zero vector \(V_{\mathrm{Z}}\) in order to synthesize \(V_{\mathrm{ref}}\). Therefore, vector PNN (\(V_{\mathrm{X}}\)), PON (\(V_{\mathrm{Y}}\)) and NNN (\(V_{\mathrm{Z}}\)) in Fig. 7 can be selected accordingly to form \(V_{\mathrm{ref}}\).

Fig. 7 Three-phase three-level inverter SVPWM vector diagram

If the dwelling time of vector \(V_{\mathrm{X}}\), \(V_{\mathrm{Y}}\) and \(V_{\mathrm{Z}}\) inside a switching period \(T_{\mathrm{sw}}\) are \(T_{\mathrm{X}}\), \(T_{\mathrm{Y}}\) and \(T_{\mathrm{Z}}\) respectively, the following functions must be satisfied:

\[{V_{\mathrm{X}}}{T_{\mathrm{X}}}+{V_{\mathrm{Y}}}{T_{\mathrm{Y}}}+{V_{\mathrm{Z}}}{T_{\mathrm{Z}}} = {V_{\mathrm{ref}}}{T_{\mathrm{sw}}}\]

(1)\[{T_{\mathrm{X}}}+{T_{\mathrm{Y}}}+{T_{\mathrm{Z}}} = {T_{\mathrm{sw}}}\]

However, it is difficult to determine \(V_{\mathrm{X}}\), \(V_{\mathrm{Y}}\) and \(V_{\mathrm{Z}}\) by the angle only, which is used in the 2-level SVPWM scheme, because the reference vector can be located in different sectors even if the angle is the same. To determine the sector, the amplitude of the reference vector is also needed, but this increases the complexity of the calculation.

Thus, [3] presented a simplified way to determine \(V_{\mathrm{X}}\), \(V_{\mathrm{Y}}\) and \(V_{\mathrm{Z}}\), using the core of 2-level SVPWM. First, the whole vector diagram shown in Fig. 7 is divided into six main sectors. Each main sector has a shape of a sub-hexagon, and all six sub-hexagons distribute continuously with a 60:math:^circ angle difference. Fig. 8 depicts sub-hexagon 1 and 2 as an example.

Fig. 8 Sub-hexagon 1 and 2 out of the divided six sub-hexagons in the whole vector diagram

After the main sector (sub-hexagon) is determined, the original vectors must be mapped into the selected main sector. The mapping algorithm follows:

\[{V'} = {V_{\mathrm{original}}-V_{\mathrm{map}}}\]

For example the original vectors in the main sector 1 are PPP (OOO, NNN), POP (ONO), PNO, PNN, PON, PPO (OON), and POO (ONN). To get a hexagon similar to the 2-level SVPWM, take POO (ONN) as the mapping vector \(V_{\mathrm{map1}} = V_{\mathrm{0}}\). After the mapping we can get the hexagon shown in Fig. 9, which is the same vector diagram as the 2-level SVPWM.

Fig. 9 Mapping from the 3-level SVPWM to a 2-level SVPWM in sub-hexagon 1

From Fig. 9, it can be seen that \(V'_{\mathrm{ref}}\) is still in the mapped sub-hexagon 1, and we can easily determine that the dwelling vectors are \(V'_{\mathrm{1}}\) and \(V'_{\mathrm{2}}\). The \(V'_{\mathrm{0}}\) can be taken as the zero vector in the 2-level SVPWM. So, we can get the following function:

(2)\[{V'_{\mathrm{1}}}{T_{\mathrm{X}}} + {V'_{\mathrm{2}}}{T_{\mathrm{Y}}} + {V'_{\mathrm{0}}}{T_{\mathrm{Z}}} = {V'_{\mathrm{ref}}}{T_{\mathrm{sw}}}\]

Note that Eq. (1) is still valid here. Combing Eq. (1) and Eq. (2), one can derive:

(3)\[({V_{\mathrm{1}}}-{V_{\mathrm{map1}}}){T_{\mathrm{X}}} + ({V_{\mathrm{2}}}-{V_{\mathrm{map1}}}){T_{\mathrm{Y}}} + ({V_{\mathrm{0}}}-{V_{\mathrm{map1}}}){T_{\mathrm{Z}}} = ({V_{\mathrm{ref}}}-{V_{\mathrm{map1}}}){T_{\mathrm{sw}}}\]

which means:

\[{V_{\mathrm{1}}}{T_{\mathrm{X}}} + {V_{\mathrm{2}}}{T_{\mathrm{Y}}} + {V_{\mathrm{0}}}{T_{\mathrm{Z}}} = {V_{\mathrm{ref}}}{T_{\mathrm{sw}}}\]

Thus, if the dwelling time of \(V'_{\mathrm{1}}\), \(V'_{\mathrm{2}}\), and \(V'_{\mathrm{0}}\) can be calculated, the original vector dwelling time can be determined. From the mapping in Fig. 9, the vector selection and the dwelling time calculation of the 3-level SVPWM are converted to 2-level SVPWM totally.

Different main sectors have different mapping vectors. Tab. 3 summarizes the mapping vector for each main sector.

Table 3 Mapping vector for each main sector

Main sector No.	Mapping vector	Element of \(\alpha\)	Element of \(\beta\)
1	POO or ONN	\(\frac{V_{\mathrm{dc}}}{3}\)	0
2	PPO or OON	\(\frac{V_{\mathrm{dc}}}{6}\)	\(\frac{\sqrt{3}V_{\mathrm{dc}}}{6}\)
3	OPO or NON	\(-\frac{V_{\mathrm{dc}}}{6}\)	\(\frac{\sqrt{3}V_{\mathrm{dc}}}{6}\)
4	OPP or NOO	\(-\frac{V_{\mathrm{dc}}}{3}\)	0
5	OOP or NNO	\(-\frac{V_{\mathrm{dc}}}{6}\)	\(-\frac{\sqrt{3}V_{\mathrm{dc}}}{6}\)
6	POP or ONO	\(\frac{V_{\mathrm{dc}}}{6}\)	\(-\frac{\sqrt{3}V_{\mathrm{dc}}}{6}\)

The main sector number can be defined by the angle of the \(V_{\mathrm{ref}}\) in the \(\alpha\)-\(\beta\) coordinate plane. For example, according to Fig. 8, the angle range of main sector 1 is [\(-\frac{\pi}{3}, \frac{\pi}{3}\)], and the angle range of main sector 2 is [0, \(\frac{2\pi}{3}\)]. Thus, the overlapped area between main sector 1 and 2 can be split into the two adjacent areas equally, in order to have monopolized angle area for each sector. Fig. 10 depicts the simplified definition of the six main sectors.

Fig. 10 Simplified definition of the six main sectors

In the 2-level SVPWM, the first step is to find the sector number which can determine the dwelling vectors. The second step is to calculate the dwelling time for each of the selected vectors. According to the principle of 3-level SVPWM, when the main sector is determined and all the vectors are mapped to the main sector, the same process done in 2-level SVPWM can be implemented to determine the sub-sector and calculate the dwelling times for each dwelling vectors. Here in this demo model, a simple and effective way is deployed [3] to calculate the duty cycle for each switching pair out of the dwelling time of each dwelling vector.

Again we take main sector 1 as an example. According to Fig. 8 there is no N status for u phase. Besides, if OON, ONO, and OOO are selected for the vector mapping, there will be no P status for the v and w phases. For the u phase, we represent the P status with 1, and the O status with 0. For v and w phases, we represent the O status with 1, and the N status with 0. Fig. 11 depicts this replacement operation. After this downsizing operation, the dwelling time for three vectors can be determined. As shown in Fig. 11, \(T_{\mathrm{X}}\) is the dwelling time of status 100, \(T_{\mathrm{Y}}\) represents the one of status 110, and \(T_{\mathrm{Z}}\) is the time for status 111 and 000.

Fig. 11 The status replacement rule downsizing 3-level vector diagram to 2-level one in main sector 1

Here we can calculate the three duty cycles for the upper switches out of the three complementary switch pairs (d1, d2, and d3), with the symmetrical PWM mode. The left side of Fig. 12 shows that effectively, the resulting 2-level vector sequence is 000 - 100 - 110 - 111- 110 - 100 - 000. Next, if we apply the same status replacement rule as in Fig. 11, we get the right part of Fig. 12. Thus we can achieve the 3-level vector sequence: ONN - PNN - PON - POO - PON - PNN - ONN.

Fig. 12 Symmetrical 2-level SVPWM applying the status replacement rule back to a 3-level SVPWM

Tab. 4 summarizes this status replacement rule for each main sector. The positive pair of power switches is Qx1 and Qx3 (x = u, v, w); the negative pair of the power switches is Qx2 and Qx4 (x = u, v, w). We also define the same status 0 and 1 for each pair as the 2-level SVPWM. So for the main sector 1, since in one switching cycle, u phase has no N status, the negative pair u phase is always 0. Similarly for the v and w phases, since they have no P status, the positive pair is always 0. That means in the main sector 1, d1 can be assigned to the positive pair of u phase (i.e. Qu1 has duty cycle of d1, and Qu3 has complementary logic to Qu1), d2 can be assigned to the negative pair of v phase (i.e. Qv2 has duty cycle of d2, and Qv4 has complementary logic to Qv2), and d3 can be assigned to the negative pair of w phase (i.e. Qw2 has duty cycle of d3, and Qw4 has complementary logic to Qw2). The process can be extended to all the six main sectors and Tab. 5 shows this duty cycle assignment rule.

Table 4 Status replacement rule for each main sector

Main sector	U phase		V phase		W phase
No.	1	0	1	0	1	0
1	P	O	O	N	O	N
2	P	O	P	O	O	N
3	O	N	P	O	O	N
4	O	N	P	O	P	O
5	O	N	O	N	P	O
6	P	O	O	N	P	O

Table 5 Duty cycle assignment rule for each main sector

Main sector	U phase		V phase		W phase
No.	Positive pair	Negative pair	Positive pair	Negative pair	Positive pair	Negative pair
	(Qu1)	(Qu2)	(Qv1)	(Qv2)	(Qw1)	(Qw2)
1	d1	1	0	d2	0	d3
2	d1	1	d2	1	0	d3
3	0	d1	d2	1	0	d3
4	0	d1	d2	1	d3	1
5	0	d1	0	d2	d3	1
6	d1	1	0	d2	d3	1

The simplified 3-level SVPWM algorithm discussed above is implemented using the C-Script block and the output provides six modulation index values for Qu1, Qu2, Qv1, Qv2, Qw1 and Qw2 individually, as summarized in Tab. 5. The complementary signal for each of them is realized by configuring the opposite Polarity in the corresponding PWM Out blocks.

Neutral-point balancing technique

The active neutral-point balancing technique implemented in this demo model is based on [4]. Neutral-point current \(i_{\mathrm{NP}}\) is denoted as the current coming out of the DC neutral point shown in Fig. 2. According to the SVPWM vector diagram shown in Fig. 7, Tab. 6 summarizes all the vectors that influence the neutral-point balance. \(i_{\mathrm{u,v,w}}\) denotes the current direction going out of the switching node of the three-level phase leg entering the grid side.

Small vectors come in pairs, e.g. POO and ONN, and they disturb the neutral point with exactly the same current value, but just the opposite sign. Furthermore, as shown in Fig. 11, POO and ONN are the new zero vectors in the downsized 2-level vector diagram in main sector 1. Therefore, the active control of neutral-point voltage lies in the manipulation of this new zero vector pair. This requires measuring the middle-point voltage (\(v_{\mathrm{mid}}\) in Fig. 2) in addition to the full DC voltage (\(v_{\mathrm{dc}}\) in Fig. 2). As a result, the total zero vector dwelling time \(T_{\mathrm{Z}}\) in Fig. 12 will be split between its 2-level “111” and “000” vectors, each proportional to its half DC voltage. Since the medium vectors disturb the neutral point and there is no vector that can be used to balance with the medium vector inside each main sector, some neutral-point variation can still be observed on the scale of each main sector. For more details and limitations of this method, please refer to [4].

Table 6 Neutral-point current \(i_{\mathrm{NP}}\) for different space vectors

Positive Small Vectors	\(i_{\mathrm{NP}}\)	Negative Small Vectors	\(i_{\mathrm{NP}}\)	Medium Vectors	\(i_{\mathrm{NP}}\)
ONN	\(i_{\mathrm{u}}\)	POO	-\(i_{\mathrm{u}}\)	PON	\(i_{\mathrm{v}}\)
PPO	\(i_{\mathrm{w}}\)	OON	-\(i_{\mathrm{w}}\)	OPN	\(i_{\mathrm{u}}\)
NON	\(i_{\mathrm{v}}\)	OPO	-\(i_{\mathrm{v}}\)	NPO	\(i_{\mathrm{w}}\)
OPP	\(i_{\mathrm{u}}\)	NOO	-\(i_{\mathrm{u}}\)	NOP	\(i_{\mathrm{v}}\)
NNO	\(i_{\mathrm{w}}\)	OOP	-\(i_{\mathrm{w}}\)	ONP	\(i_{\mathrm{u}}\)
POP	\(i_{\mathrm{v}}\)	ONO	-\(i_{\mathrm{v}}\)	PNO	\(i_{\mathrm{w}}\)

Simulation

This model can run both, in offline mode on a computer or in real-time mode on the PLECS RT Box. For the real-time operation, one RT Box (referred to as “Plant + Controller”) needs to be set up as demonstrated in Fig. 13.

Note

To utilize the FlexArray solver on an RT Box 2, 3 or 4, the Electrical Model Settings block connected to the power converter topology has to be configured as Target: FlexArray. Please see the model initialization commands of this demo for more details.

Fig. 13 Hardware configuration for the real-time operation on a single RT Box

Please follow the instructions below to run a real-time model on a single RT Box:

1. Connect the Analog Out interface to the Analog In interface with one DB37 cable, and the Digital Out interface to the Digital In interface with another DB37 cable (as shown in Fig. 13).

2. From the System tab of the Coder options… window, select the “Plant + Controller” subsystem and Build it onto the RT Box.

3. Once the model is uploaded, from the External Mode tab of the Coder options… window, Connect to the RT Box and Activate autotriggering.

Note

As shown below, the Manual Signal Switch in the “Controller” task in its default “up” position enables switching, once the model is up and running.

Changing it to the “down” position trips all PWMs into the safe state, and resets the id-iq PI Controller integral part to its initial condition.

The PWM safe state is configured in the Protection tab of each PWM Out block.

Key waveforms can be observed in the “Measurements” Scopes individually placed in the plant topology and the “Controller” task. Since the neutral-point balancing technique is implemented in the controller, the middle-point DC voltage can be controlled at around \(400\,\mathrm{V}\) operating at steady state even though the initial voltages on the upper and lower DC capacitors are \(450\,\mathrm{V}\) and \(350\,\mathrm{V}\) , respectively. A DC voltage step change can be applied on the “Sun” Constant block, such as from 1 to 1.2. This implies a sun radiation change on the PV panels. Fig. 14 captures the response to such an event on the inverter side. One can see that the middle-point DC voltage rises from \(400\,\mathrm{V}\) to \(480\,\mathrm{V}\), and stabilizes afterwards. Accordingly, grid currents are controlled to deliver the same d-q axis currents after short dynamics.

Fig. 14 Real-time simulation result for inverter under DC voltage rise

Next, keeping the DC voltage at the default value of \(800\,\mathrm{V}\), on the controller side of the “Virtual damping resistor”, the Gain block can be changed to 85 % of the original value (\((L_{\mathrm{c}}+L_{\mathrm{g}})/L_{\mathrm{g}}*R_{\mathrm{D}}\)). A moderate amount of ringing in current waveforms can be observed due to inadequate damping. This is demonstrated in Fig. 15. Changing the “Virtual damping resistor” gain back to the original value, this unwanted ringing can be eliminated.

Fig. 15 Real-time simulation result for inverter with poorly damped virtual resistor

In the end, since PI controllers are designed individually for d-q axis currents, a d-axis current reference step-down is performed by changing the “\(I_{\mathrm{fd}}^*\)” Constant block, such as to 80 % of its original value. Fig. 16 captures this reference step. The grid currents are controlled to the new d-axis reference value, while maintaining a power factor of 1 due to the unchanged q-axis current reference of 0.

Fig. 16 Controller task side real-time simulation result for inverter under d-axis current reference step

Conclusion

This RT Box demo model demonstrates a three-level grid-connected NPC inverter under closed-loop control with d-q axis continuous PI current controllers. The demo model can run in both offline simulation and real-time operation for hardware-in-the-loop tests or rapid control prototyping. The plant model runs with a discretization step size of \(5\,\mu\mathrm{s}\) on the RT Box. The controller task runs with a discretization step size of \(50\,\mu\mathrm{s}\), which is the size of the switching period.

Bibliography

[1]

R. Teodorescu, M. Liserre and P. Rodriguez, “Grid converters for photovoltaic and wind power systems”, pp. 289-311, IEEE, Wiley, 2011.

[2]

R. W. Erickson, “Optimal single resistors damping of input filters”, APEC ‘99, Fourteenth Annual Applied Power Electronics Conference and Exposition, vol.2, pp. 1073-1079, March 1999.

[3]

V. Xue, “Center-Aligned SVPWM Realization for 3-Phase 3-Level Inverter (Application Report)”, Texas Instruments, October 2012.

[4]

N. Celanovic and D. Boroyevich, “A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters”, IEEE Transactions on Power Electronics, vol. 15, no. 2, pp. 242-249, March 2000.