PWM Capture
Purpose
Averages a digital input over the period of a model step.
Description
The PWM Capture output represents the percentage of time during which a digital input signal was active over the last model step period. The PWM capture active polarity can be set channel wise. During an offline simulation the percentage time in the active state within the last simulation step is calculated.
The RT Box FPGA sample time of the incoming PWM is:
\(3.75\,\mathrm{ns}\) (clock frequency of \(266\,\mathrm{MHz}\)) for RT Box 1 or CE;
\(3.33\,\mathrm{ns}\) (clock frequency of \(300\,\mathrm{MHz}\)) for RT Box 2, 3 or 4.
Note that for step size larger than \(15.3\,\mathrm{\mu s}\) on RT Box 1 or CE, and \(13.6\,\mathrm{\mu s}\) on RT Box 2, 3 or 4, the following resolution will be used: \(7.5\,\mathrm{ns}\) for RT Box 1 or CE, \(6.66\,\mathrm{ns}\) for RT Box 2, 3 or 4.
Next for each multiple of these times, the sample rate changes again. This means, e.g. for RT Box 2, 3 or 4, for step size larger than \(27.2\,\mathrm{\mu s}\), \(10\,\mathrm{ns}\) resolution is used; for step size larger than \(40.8\,\mathrm{\mu s}\), \(13.3\,\mathrm{ns}\) resolution is used; etc.
Parameters
- Digital input channel(s)
Index of the digital input channel. For vectorized input signals a vector of input channel indices must be specified.
- Channel(s) active polarity
Active level of a digital input. For vectorized input signals either a scalar or a vector with the length of the input channels must be specified.
- Offline behavior
Configures the averaging interval for the offline simulation to match the connected power module configuration. Possible values are Sub-cycle average for power modules that use sub-cycle averaging or Nanostep for power modules that employ a Nanostep solver.
- Input characteristic
Specifies whether an internal pull-up or pull-down resistor is connected to the digital input.