PWM Out (Variable)

Purpose

Generate PWM signals with variable frequency and variable phase-shift.

Description

The PWM Out (Variable) block generates PWM signals on one or multiple digital output channels of the RT Box. The modulation index for each channel must be provided via the input signal \(m\), which is a vectorized signal if the block uses multiple channels.

The carrier frequency \(f_\textrm{c}\) is common to all channels of the same block. It can be controlled during the simulation using the scalar input signal \(f_\textrm{c}'\). The resulting carrier frequency \(f_\textrm{c}\) is calculated as the product of the nominal carrier frequency specified in the block parameters and the input signal \(f_\textrm{c}'\). For a constant carrier frequency, a constant value 1 must be fed into the block. If the PWM generation is synchronized to the simulation steps of the RT Box, the carrier frequency is rounded to the nearest integer multiple of the simulation frequency.

The phase shift between the carriers of the individual PWM channels can be controlled with the vectorized input signal \(ph'\). Each element of \(ph'\) specifies the phase delay of the PWM carrier in the corresponding channel. The delay is given in p.u. of the carrier period and must lie between 0 and 1.

By enabling the “Variable turn-on delay mode” (in the advanced parameters section), the input signal \(ph'\) gets replaced with input signal \(d'\), that controls the turn-on delay (in seconds) for the individual PWM channels.

PWM generation limits

In order to understand the operational limits of the PWM generation an overview is given as follows:

The PWM generation ratings (i.e. maximum/minimum operating frequencies, maximum/minimum duty cycle resolution, etc.) depend on the selected nominal carrier frequency specified in the block parameters.

The PRD value of each PWM carrier signal is a 16-bit number. This sets a limit on the maximum PWM carrier period (minimum PWM carrier frequency) to a length of \(2^{16}\) FPGA clock periods. Nevertheless, the maximum PWM carrier period can be increased, by increasing the FPGA clock period, with the use of a prescaler. The prescaler is selected as the minimum integer so that the nominal carrier frequency specified in the block parameters can be realised.

The minimum achievable PWM period (maximum PWM frequency) is set to be 20 FPGA clock periods. The maximum and minimum PWM carrier frequencies can be calculated as follows:

\[f_{\mathrm{min}} = \frac{1}{T_{\mathrm{max}}}, \ \ \ T_{\mathrm{max}} = \frac{2^{\mathrm{prescaler}}}{f_{\mathrm{FPGA}} }\cdot 2^{16}.\]

\[f_{\mathrm{max}} = \frac{1}{T_{\mathrm{min}}}, \ \ \ T_{\mathrm{min}} = \frac{2^{\mathrm{prescaler}}}{f_{\mathrm{FPGA}} }\cdot 20.\]

The duty-cycle, frequency, and phaseshift resolution will depend on the PWM carrier frequency being employed. The lowest resolution is obtained when operating at the highest PWM frequency. In case of a sawtooth carrier the lowest resolution is \(1/20 = 5 \%\), while the highest is \(2^{-16} = 0.00153 \%\). In case of a symmetrical carrier, the resolution is half of the sawtooth carrier resolution.

When frequency modulation is employed, the following table shows the maximum and minimum operating frequencies depending on the selected nominal carrier frequency for each of the RT Box models.

Table 16 RT Box 2/3/4 with 150 MHz FPGA clock frequency

Selected nominal carrier frequency	Minimum operating frequency	Maximum operating frequency	Duty cycle resolution
\(2.288\,\mathrm{kHz} < f_\textrm{c} < 7.500\,\mathrm{MHz}\)	\(2.288 \, \mathrm{kHz}\)	\(7.500\,\mathrm{MHz}\)	\(6.667\,\mathrm{ns}\) (prescaler = 0)
\(1.144\,\mathrm{kHz} < f_\textrm{c} < 2.288\,\mathrm{kHz}\)	\(1.144\,\mathrm{kHz}\)	\(3.750\,\mathrm{MHz}\)	\(13.33\,\mathrm{ns}\) (prescaler = 1)
\(572.2\,\mathrm{Hz} < f_\textrm{c} < 1.144\,\mathrm{kHz}\)	\(572.2\,\mathrm{Hz}\)	\(1.875\,\mathrm{MHz}\)	\(26.67\,\mathrm{ns}\) (prescaler = 2)
\(286.1\,\mathrm{Hz} < f_\textrm{c} < 572.2\,\mathrm{Hz}\)	\(286.1\,\mathrm{Hz}\)	\(937.5\,\mathrm{kHz}\)	\(53.33\,\mathrm{ns}\) (prescaler = 3)
\(143\,\mathrm{Hz} < f_\textrm{c} < 286.1\,\mathrm{Hz}\)	\(143\,\mathrm{Hz}\)	\(468.7\,\mathrm{kHz}\)	\(106.7\,\mathrm{ns}\) (prescaler = 4)
\(71.52\,\mathrm{Hz} < f_\textrm{c} < 143\,\mathrm{Hz}\)	\(71.52\,\mathrm{Hz}\)	\(234.4\,\mathrm{kHz}\)	\(213.3\,\mathrm{ns}\) (prescaler = 5)
\(35.7\,\mathrm{Hz} < f_\textrm{c} < 71.52\,\mathrm{Hz}\)	\(35.7\,\mathrm{Hz}\)	\(117.26\,\mathrm{kHz}\)	\(426.7\,\mathrm{ns}\) (prescaler = 6)

Table 17 RT Box CE/1 with 133 MHz FPGA clock frequency

Selected nominal carrier frequency	Minimum operating frequency	Maximum operating frequency	Duty cycle resolution
\(2.035\,\mathrm{kHz} < f_\textrm{c} < 6.667\,\mathrm{MHz}\)	\(2.035\,\mathrm{kHz}\)	\(6.667\,\mathrm{MHz}\)	\(7.5\,\mathrm{ns}\) (prescaler = 0)
\(1.017\,\mathrm{kHz} < f_\textrm{c} < 2.035\,\mathrm{kHz}\)	\(1.017\,\mathrm{kHz}\)	\(3.333\,\mathrm{MHz}\)	\(15\,\mathrm{ns}\) (prescaler = 1)
\(508.6\,\mathrm{Hz} < f_\textrm{c} < 1.017\,\mathrm{kHz}\)	\(508.6\,\mathrm{Hz}\)	\(1.667\,\mathrm{MHz}\)	\(30\,\mathrm{ns}\) (prescaler = 2)
\(254.3\,\mathrm{Hz} < f_\textrm{c} < 508.6\,\mathrm{Hz}\)	\(254.3\,\mathrm{Hz}\)	\(833.3\,\mathrm{kHz}\)	\(60\,\mathrm{ns}\) (prescaler = 3)
\(127.2\,\mathrm{Hz} < f_\textrm{c} < 254.3\,\mathrm{Hz}\)	\(127.2\,\mathrm{Hz}\)	\(416.6\,\mathrm{kHz}\)	\(120\,\mathrm{ns}\) (prescaler = 4)
\(63.6\,\mathrm{Hz} < f_\textrm{c} < 127.2.\,\mathrm{Hz}\)	\(63.6\,\mathrm{Hz}\)	\(208.3\,\mathrm{kHz}\)	\(240\,\mathrm{ns}\) (prescaler = 5)
\(31.8\,\mathrm{Hz} < f_\textrm{c} < 63.6\,\mathrm{Hz}\)	\(31.8\,\mathrm{Hz}\)	\(104.2\,\mathrm{kHz}\)	\(480\,\mathrm{ns}\) (prescaler = 6)

The tables show the frequency values for prescaler values from 0 to 6. Since the prescaler is a 4-bit number, and its maximum value is 15, the minimum achievable operating frequency would be 0.0621 Hz for RT Box 1 and CE, and 0.07 Hz for RT Box 2, 3 and 4.

Note

Keep in mind that the prescaler is calculated once during the compilation process, and it is not modified during runtime. Therefore, in case of variable frequency operation, the nominal frequency should be selected as the lowest frequency required during operation.

PWM implementation details

To understand the PWM generation for variable frequency and variable phase-shift, an overview of the internal implementation is given:

Each PWM channel has its own a ramp generator for a carrier signal. In case of a sawtooth carrier, the carrier signal ramps up with a constant slope from its initial value 0 to reach the value PRD at the end of the PWM period. When it reaches PRD, the carrier is instantaneously reset to 0. The period PRD is computed as the inverse of the current carrier frequency \(f_\textrm{c}\). In case of a symmetrical carrier, the rising ramp reaches its maximum value PRD/2 after half the PWM period and the carrier then ramps down to reach 0 at the end of the PWM period.

The modulation index for each channel is mapped from its original input range defined by the carrier limits to a compare value CMP. CMP has a minimum value of 0 and a maximum value of PRD for sawtooth carriers or PRD/2 for symmetrical carriers. If the parameter Polarity of a channel is set to 0 its PWM output becomes high whenever CMP is greater than the carrier signal.

Fig. 9 Update schemes for modulation index with sawtooth carrier

Fig. 10 Update schemes for modulation index with symmetrical carrier

The user can choose how often the CMP value is updated. If the parameter Update is set to “Immediately”, CMP will be updated asynchronously whenever a new modulation index has been computed in a model step. This can be helpful if the simulation step size is much shorter than the PWM period. For updating CMP synchronously after every complete PWM period, the parameter Update must be set to “At carrier minimum”. In case of a symmetrical carrier, there are two additional options available for synchronously updating CMP: If the parameter Update is set to “At carrier maximum”, CMP will be refreshed in the middle of the PWM period at the tips of the carrier. If set to “At carrier minimum and maximum” the update will be performed twice in every PWM period.

If a PWM Out (Variable) block contains multiple output channels, the first channel automatically becomes the primary channel while the other channels are configured as secondary. Every time the ramp generator of the primary channel becomes 0, the primary channel transmits a synchronization signal to the secondary channels of the same block. When this happens, the ramp generators of the secondary channels are set to their initial values computed from the input signal \(ph'\) to achieve the desired phase shift.

Fig. 11 Phase-shift variation with different carrier types

Note

The values at input signal \(ph'\) for all the secondary channels (i.e. all elements other than the first) represent their individual phase delay in p.u. in relation to the primary channel.

In addition, if required, the first element of the input signal \(ph'\) can be used to generate a phase delay for the primary channel carrier in relation to the CPU simulation step if the parameter Synchronization with model step is set to Enabled.

The phase delays between multiple PWM Out (Variable) blocks are only defined if the blocks have the same Nominal carrier frequency, share a constant frequency input signal \(f_\textrm{c}'\) and are synchronized with model step of the RT Box.

With the synchronization signal from the primary channel, the PWM period is updated as well. A new value of PRD is computed from the carrier frequency and applied to all channels. A change in PRD will change the compare value CMP in order to obtain the desired modulation index.

Fig. 12 Carrier frequency variation with different carrier types

Parameters

General

Digital output channel(s)

Index of the digital output channel. For vectorized output signals a vector of output channel indices must be specified.

Carrier type

Selects the carrier waveform, either sawtooth or symmetrical.

Nominal carrier frequency

The nominal frequency of the carrier in hertz (Hz). The actual PWM frequency is equal to the nominal carrier frequency multiplied by the input signal \(f_\textrm{c}'\).

Carrier phase shift

The phase shift of the carrier signal, in p.u. of the carrier period. The parameter can be either a scalar or a vector with the same width as the number of output channels. This field is only available when “Variable turn-on delay mode” is enabled.

Carrier limits

The range of the carrier signal. The default is [-1 1].

Turn-on delay

Turn-on delay of the PWM output in seconds. This field is not available when “Variable turn-on delay mode” is enabled.

Polarity

The polarity of the PWM output determines whether the PWM signal is in on-state (value 1) or off-state (value 0) when the modulation index exceeds the carrier. The parameter can be either a scalar or a vector with the same width as the number of output channels.

Update

If “On carrier minimum”, “On carrier maximum” or “On carrier minimum/ maximum” is selected the modulation index will be sampled when the carrier reaches its minimum or maximum values. If “Immediately” is selected the modulation index will be updated after each simulation step of the RT Box.

Synchronization with model step

If “Enabled” is selected and the discretization step size is an integer multiple of the PWM period, the PWM generation will be synchronized with the simulation steps of the RT Box. If the block is placed inside of a task frame, the step size of the task frame will be used for synchronization.

Protection

Safe state

Specifies the state to which the output signal is set when the Powerstage Protection Unit is activated. A value of 0 indicates a low signal value (0 Volts), a value of 1 indicates a high signal value (3.3V or 5V, depending on the output voltage level). The parameter can be either a scalar or a vector with the same width as the number of output channels. The Safe state is also applied before the real-time simulation is started and after it is stopped (manually or due to a runtime error).

Powerstage protection unit

Specifies the Powerstage Protection Unit that is associated with this PWM block. If the Powerstage Protection feature is not needed, the option can be set to “None”. Otherwise, up to four Powerstage Protection Unit can be configured per model. If a Powerstage Protection Unit is selected that is not configured in the model, PLECS shows a warning when running an offline simulation or generating code. See Powerstage Protection Unit for details.

Advanced

Active polarity for turn-on delay

Specifies whether the turn-on delay is applied during the rising edge (1, default) or the falling edge (0) of the PWM signal. The polarity should be changed to 0 only for switches that are turned on when the output voltage is 0 Volts. This parameter has no influence on the polarity nor the safe state of the output signal.

Variable turn-on delay mode

When “Enabled” is selected, the input signal \(ph'\) gets replaced with input signal \(d'\), that controls the turn-on delay (in seconds) for the individual PWM channels. Additionally, the field “Minimal turn-on delay” allows to specify the lower limit, for safety reasons. The upper limit of the turn-on delay is about 0.4ms. Furthermore, a field to specify constant carrier phase shift per channel is available in the general parameter section.

Minimal turn-on delay

Minimal turn-on delay of the PWM output in seconds. This field is only available when “Variable turn-on delay” is enabled.

ADC trigger output

Allows to generate an ADC trigger output, either “On carrier minimum”, “On carrier maximum” or “On carrier minimum/maximum”. This block output is hidden when “Disabled” is selected. Otherwise, the ADC output is intended to get connected to a trigger input of an Analog In block.