Resolver Out
Purpose
Emulates a two-pole transmitter resolver by modulating the amplitude of an external exciter voltage.
Description
The Resolver Out block emulates a two-pole transmitter resolver. A differential exciter voltage is fed into the RT Box and multiplied by the sine and cosine of the angle signal at the block’s input terminal. The angle is measured in rad. The resulting output voltages are available as differential signals on the +COSOUT, -COSOUT, +SINOUT and -SINOUT pins at the Resolver Out connector. A common DC offset can be added to the differential output signals to adjust the voltage range for resolver-to-digital converter that only allow positive input voltages (as, for example, the AD2S1210 used for the Resolver In in the RT Box 2, 3 and 4).
Absolute maximum rating for +EXCIN and -EXCIN pin is -24 \(\mathrm{V}\) to +24 \(\mathrm{V}\) with respect to GND (electrical damage may occur if the maximum rating is exceeded). For correct functionality, neither +EXCIN nor -EXCIN pin may exceed -10 \(\mathrm{V}\) to +10 \(\mathrm{V}\). Additionally, +EXCIN and -EXCIN input should be chosen such that \(|(\mathrm{+EXCIN}) - (\mathrm{-EXCIN})|/2 * \mathrm{Gain} + \mathrm{Offset} < 10 \, \mathrm{V}\) at all times (output will be incorrect otherwise).
Outputs are generated as follows:
The RT Box 2 or 4 provides one resolver output, and the RT Box 3 provides two of them. There is no resolver output available on the RT Box 1 or CE.
Parameters
- Resolver module
Specifies which resolver output to use. The second resolver input is available on the RT Box 3 only.
- Gain
The exciter voltage may be attenuated by the given factor in addition to the sine/cosine attenuation. The maximum resolver resolution is achieved with a gain of 1.
- DC output offset
Specifies an additional offset voltage to be applied to the +COSOUT, -COSOUT, +SINOUT and -SINOUT signals. The value is specified in Volt.
- Interpolation
If interpolation is enabled, the +COSOUT, -COSOUT, +SINOUT and -SINOUT signals are generated in smaller interpolated steps between simulation steps of the RT Box. If an FPGA simulation is running, the interpolation step size is identical to the FPGA simulation step size. If no FPGA simulation is running, the interpolation step size is automatically selected as the minimum integer fraction of the CPU discretization time that is supported by the RT Box.