SPI Controller

Purpose

Implement SPI communication via digital outputs/inputs.

SPI enables synchronous communication with peripheral devices. The SPI Controller block provides a clock signal which generates a configurable number of clock pulses. Data is read and written on the edges of the clock signal. For high-speed communication, the clock output signal can be looped back to an input to provide a clock input signal which is synchronized to the input data.

Description

The RT Box contains two independent SPI modules that can be configured either as an SPI controller or SPI peripheral. When acting as an SPI controller the module provides a single clock and a single chip select signal. The chip select signal is held low during the data transfer. Each SPI module can receive and transmit data on up to four data lines in parallel.

An output value of 1 at the v port indicates that the appropriate number of clock edges has been detected on the feedback clock input and valid data is present on the other output ports. If the number of detected clock edges does not match the output value at the v port is set to 0 and the data output ports are not updated, i.e. they retain their values from the previous simulation step. If the skew-matched clock input is disabled, the output of the v port is always 1.

The RT Box contains two independent SPI units. Each unit may be used as SPI Controller or SPI Peripheral.

Parameters

Setup

SPI clock frequency [Hz]

Clock frequency used for data transmission [20e3 … 40e6]. Each clock phase is rounded to the nearest integer multiple of \(4\,\mathrm{ns}\).

Delay first clock pulse after CS active [ticks]

Number of SPI clock periods between CS edge and first clock edge.

Hold CS active after last clock pulse [ticks]

Number of SPI clock periods between last clock edge and CS edge.

Delay CS after simulation step

Defines the begin of the SPI transmission within a simulation step. If “Minimum” is selected the transmission starts immediately when data is available to minimize the output data latency. For “Maximum” the transmission delay is computed to minimize the input data latency. “Specify delay time” is used to adjust the delay manually.

CS delay time [s]

Time for manual delay.

Mode [CPOL, CPHA]

SPI mode as a combination of clock polarity (CPOL) and clock phase (CPHA). CPOL controls whether the clock signal is high (1) or low (0) when idle. CPHA controls whether data is shifted in and out on the rising or falling edge of the clock signal. The following table summarizes the combination of clock polarity and phase:

Table 18 SPI Modes

Mode	CPOL	CPHA	Output Edge	Data Capture
SPI_MODE0	0	0	Falling	Rising
SPI_MODE1	0	1	Rising	Falling
SPI_MODE2	1	0	Rising	Falling
SPI_MODE3	1	1	Falling	Rising

Bits per word

Length of a single data word during transmission. Depending on this setting the input signals are interpreted as either uint8 or uint16.

Bit order

Defines if LSB or the MSB is transmitted and received first.

Skew-matched clock input

Enables the clock input for clock feedback. Typically required if the signal delay from the controller output to its input exceeds half a SPI clock period. If it exceeds a full period the parameter “Hold CS active after last clock pulse [ticks]” should also be increased.

Number of parallel data channels

Specifies how many of the four available data channels are used.

Words per transmission (up to 127)

Configures number of transmitted data words in each simulation step.

Sample time

The sample time determines how often data is sent (and received) on the SPI bus. It can be set to an integer multiple of the base step size. Use 0 to transfer data in every simulation step and -1 to inherit the sample time from the blocks feeding data into the SPI block.

Input

Digital input channel for skew-matched SPI clock

Clock input for clock feedback.

Digital input channel(s) for SPI data

Data input (MISO) channel/s as a scalar or vector. The width of this parameter corresponds to “Number of parallel data channels”. “-1” denotes an unused input.

Output

Digital output channel for SPI clock

Clock output channel.

Digital output channel for CS

Chip select output channel.

Digital output channel(s) for SPI data

Data output (MOSI) channel/s as a scalar or vector. The width of this parameter corresponds to “Number of parallel data channels”. “-1” denotes an unused output.