SPI Peripheral

Purpose

Implement SPI communication via digital outputs/inputs.

SPI enables synchronous communication with peripheral devices. Data is read and written on the edges of the clock signal while the chip select input is low. For high-speed communication, the internally processed clock signal, which is synchronized to the output data, can be provided on an output.

Description

The RT Box contains two independent SPI modules that can be configured either as an SPI controller or SPI peripheral. When acting as an SPI peripheral the module provides a single clock input and a single chip select input. The chip select signal must be set to low during the data transfer.

Each SPI module can receive and transmit data on up to four data lines in parallel.

The operation of the SPI peripheral is not synchronized with the simulation. A new SPI cycle is started with the falling edge of the chip select input signal. During the SPI cycle, the device sends the data that was last received at its model inputs. To ensure data integrity, once the SPI cycle is started, the send data cannot be changed by the simulation model until the SPI cycle is complete. After the SPI cycle is complete and the correct number of clock pulses have been received, the received data from the SPI bus will be available at the model outputs of the block in the next simulation step. The availability of new data is indicated by a 1 at the v connector. As long as no new data is received on the SPI bus, the previously received data is available at the model outputs of the block.

The RT Box contains two independent SPI units. Each unit may be used as SPI Controller or SPI Peripheral.

Parameters

Setup

SPI clock frequency (approx) [Hz]

The approximate frequency of the SPI clock. This value is used for an internal error correction

Mode [CPOL, CPHA]

SPI mode as a combination of clock polarity (CPOL) and clock phase (CPHA). CPOL controls whether the clock signal is high (1) or low (0) when idle. CPHA controls whether data is shifted in and out on the rising or falling edge of the clock signal. The following table summarizes the combination of clock polarity and phase:

Table 19 SPI Modes

Mode	CPOL	CPHA	Output Edge	Data Capture
SPI_MODE0	0	0	Falling	Rising
SPI_MODE1	0	1	Rising	Falling
SPI_MODE2	1	0	Rising	Falling
SPI_MODE3	1	1	Falling	Rising

Bits per word

Length of a single data word during transmission. Depending on this setting the input signals are interpreted as either uint8 or uint16.

Bit order

Defines if LSB or the MSB is transmitted and received first.

Skew-matched clock output

Enables a feedback clock output, typically required for SPI frequencies above \(5\,\mathrm{MHz}\) if the connected SPI controller provides an input for a feedback clock. The feedback clock is synchronized with the data output signals.

Number of parallel data channels

Specifies how many of the four available data channels are used.

Words per transmission (up to 127)

Configures number of transmitted data words in each simulation step.

Sample time

The sample time determines how often the SPI data is updated. It can be set to an integer multiple of the base step size. Use 0 to transfer data in every simulation step and -1 to inherit the sample time from the blocks feeding data into the SPI block.

Input

Digital input channel for SPI clock

SPI clock input.

Digital input channel for CS

Chip select input channel.

Digital input channel(s) for SPI data

Data input (MOSI) channel/s as a scalar or vector. The width of this parameter corresponds to “Number of parallel data channels”. “-1” denotes an unused input.

Output

Digital output channel for skew-matched SPI clock

SPI feedback clock output channel.

Digital output channel(s) for SPI data

Data output (MISO) channel/s as a scalar or vector. The width of this parameter corresponds to “Number of parallel data channels”. “-1” denotes an unused output.