Running Simulations on the FPGA

Depending on the RT Box model, two distinct methods are available for executing an electrical model or the time-critical parts of it on the FPGA.

The Nanostep solver enables simulations with ultra-small simulation step sizes for certain parts of an electrical model.

The FlexArray solver allows to simulate complete electrical systems on the FPGA, delivering high update rates and low latency. Both solvers run independently and can even be combined on RT Box 2, 3 and 4.

Nanostep solver

The Nanostep solver uses ultra-small simulation step sizes for controlling common power architectures, supporting MHz-level switching frequencies. Each simulation step includes sampling, calculation, and diode switch state determination. On RT Box 2, 3 and 4 the simulation time step is just \(4\,\mathrm{ns}\), on RT Box 1 and CE it is \(7.5\,\mathrm{ns}\).

With the Nanostep solver, only the time-critical part of a circuit is calculated with nanostep resolution. The remaining part of the system is calculated either on the CPU or the FlexArray solver.

The power modules supported by the Nanostep solver can be found in the Nanostep category of the PLECS components library. At least one Nanostep power module must be present in the model to use the Nanostep solver. To run the power module on a Nanostep solver, the Configuration parameter of the power module must be set to “Nanostep”.

The top line of the display of an RT Box 2, 3 or 4 indicates an active Nanostep solver by displaying the step size of the Nanostep solver before the FlexArray / CPU update rate, e.g. “\(4\,\mathrm{ns} / 250\,\mathrm{ns}\)”. An active Nanostep solver is also indicated in the web interface of the RT Box.

The number of Nanostep power modules that can be simulated within one model is limited. Each Nanostep power module is associated with a weight (a simple dual active bridge, for example, has weight of 1, a full-bridge resonant converter a weight of 3 - see the documentation of the respective power modules). RT Box 2, 3 and 4 allow the simulation of Nanostep power modules with a total weight sum of 6, for RT Box CE and 1 the total weight sum is limited to 3.

FlexArray solver

RT Box 2, 3 and 4 allow to run simulations on the FPGA using the FlexArray solver. Depending on the complexity of the model, this allows step sizes below \(100\,\mathrm{ns}\).

Only the electrical domain of a PLECS model can be run on the FlexArray solver. This usually comprises PWM Capture blocks, an electrical circuit with power modules, and meters that are connected to Analog Out blocks. The control part of the model will always be simulated on the CPU.

When a simulation is running using the FlexArray solver, the analog outputs of the RT Box are updated after each FlexArray solver step, but no faster than every \(200\,\mathrm{ns}\).

Enabling the FlexArray solver

Whether an electrical circuit is simulated on the CPU or the FlexArray solver is controlled by the Electrical Model Settings block. Place the block on the schematic and connect it to the electrical circuit that should be simulated on the FlexArray solver. The Target parameter controls whether the code for this circuit is generated for the CPU or the FlexArray solver.

Prerequisites

Code generation for the FlexArray solver is only supported for circuits based on Power Modules. Additionally, the following discrete Power Semiconductors and Switches are supported:

  • Diode

  • Thyristor

  • Triac

  • Switch

  • Double Switch

  • Triple Switch

  • Breaker

Power Modules must be connected directly to PWM capture blocks.

The FlexArray solver uses a non-ideal switch model. Once a circuit is configured for FlexArray, all switches use the non-ideal switch model automatically, regardless of their Switch model parameter.

To facilitate updates of the analog outputs with the full rate of the FlexArray solver step sizes, Meters (e.g. Voltmeters, Ammeters) must be connected directly to AnalogOut blocks. Exemptions are additional gain or offset blocks in the signal path.

Minimizing the FlexArray solver step size

The calculation time of one simulation step of the FlexArray solver depends on the complexity of the model. It does not vary from one step to the next.

The FlexArray solver step size is automatically calculated as the minimum integer fraction of the CPU discretization time that is larger than the required calculation time. The calculated step size is shown in the web interface and the upper right corner of the front display of the RT Box.

For reference, the smallest possible FlexArray solver step size for the given model is displayed in the diagnostics messages in the web interface of the RT Box. This value may be used to choose a suitable CPU discretization time (as an integer multiple of the smallest possible FPGA simulation time) to achieve the smallest possible time step.