JK Flip-flop
Purpose
Implement edge-triggered JK flip-flop
Library
Control / Logical
Description
The JK flip-flop changes its output when an edge in the clock signal is detected according to the following truth table:
J |
K |
Q |
/Q |
|---|---|---|---|
0 |
0 |
No change |
No change |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
\(/Q_\text{prev}\) |
\(Q_\text{prev}\) |
As long as no edge is detected in the clock signal the outputs remain stable.
When a trigger occurs and \(J = K = 1\), the outputs are toggled, i.e. they change from \(1\) to \(0\) or vice versa.
The inputs \(J\) and \(K\) are latched, i.e. when a triggering edge in the clock signal is detected the values of \(J\) and \(K\) from the previous simulation step are used to set the output. In other words, \(J\) and \(K\) must be stable for at least one simulation step before the flip-flop is triggered by the clock signal.
Parameters
- Trigger edge
The direction of the edge on which the inputs are read.
- Initial state
The state of the flip-flop at simulation start.
Probe Signals
- J
The input signal \(J\).
- K
The input signal \(K\).
- Clk
The clock input signal.
- Q
The output signals \(Q\).
- /Q
The output signals \(/Q\).