SPI Slave

Purpose

Implement SPI Slave

Library

STM32

Description

For a detailed description of the SPI protocol and signals, refer to the SPI Master block.

The SPI Slave is synchronized to the clock generated by the SPI Master. The SPI Master uses a dedicated active-low chip-select signal that enables the MISO and MOSI ports of the SPI Slave.

The data to be transmitted is provided at the input TX and the data received is available at the output RX. An output value of 1 at the v port indicates a valid data exchange with the SPI Master.

If the SPI RX port receives new data before the previous data has been read, the existing data will be overwritten and lost. If this occurs, the output o turns \(1\) to indicate an overrun error.

There are two considerations to note when overrun errors occur:

• The master is not allowed to start transmitting before the slave is up and running. If the slave is booting up while the master is transmitting, then it may receive an incomplete first message, from which it will not be able to recover.

• In order to avoid overruns, the SPI Slave block must be executed faster than the rate at which the SPI Master is sending data.

Parameters

Setup

SPI module

Selects the SPI module to use.

Bits per word (4-16)

Defines the length of a single data word during transmission. The allowed length is 4 to 16 bits per word.

Mode [CPOL, CPHA]

Defines four SPI clocking modes, controlled by clock polarity (CPOL) and clock phase (CPHA) bits. CPOL controls whether the clock signal is high (1) or low (0) when idle. CPHA controls whether data is shifted in and out on the rising or falling edge of the clock signal. The following table summarizes ST’s convention of clock polarity and phase according to the standard SPI operating modes:

Table 2 SPI Clocking Modes

Mode	CPOL	CPHA	SPI Clock Scheme
SPI_MODE0	0	0	Rising edge without delay
SPI_MODE1	0	1	Rising edge with delay
SPI_MODE2	1	0	Falling edge without delay
SPI_MODE3	1	1	Falling edge with delay

Words per transmission

Configures the number of transmitted data words in each simulation step.

Offline simulation

Enables or disables data inspection in an offline simulation. If set to enable, terminals are added to the subsystem in the top-level schematic. If set to disable, no such terminals are added to the subsystem.

GPIO Settings

SCK Port

Selects the port name of the clock frequency signal.

SCK Pin

Defines the pin number of the clock frequency signal.

MISO Port

Selects the port name of the MISO signal.

MISO Pin

Defines the pin number of the MISO signal.

MOSI Port

Selects the port name of the MOSI signal.

MOSI Pin

Defines the pin number of the MOSI signal.

CS Port

Selects the port name of the chip-select signal.

CS Pin

Defines the pin number of the chip-select signal.