Flying Capacitor Half Bridge

Purpose

Multi-level inverter half bridge with flying capacitors and a Sub-cycle average implementation

Library

Electrical / Power Modules

Description

../../_images/powermodule_flyingcap.svg

This Power Module implements a multi-level inverter half bridge with flying capacitors. The vectorized DC side terminals for the capacitors are ordered from outer to inner voltage levels. The vectorized control inputs are ordered from the top to the bottom switch.

The component offers two configurations:

Sub-cycle average

Each gate input is controlled by a floating-point number with values between \(0\) and \(1\), representing the relative on-time of the corresponding semiconductor over one simulation step, as described in Sub-cycle Averaging. The DC side of the converter has current source behavior and must be connected to a positively biased capacitor or voltage source. The AC side is typically connected to an inductor.

In Sub-cycle average configuration, C code generated from this component is suitable for real-time simulations on the RT Box, where it is executed on the CPU or FlexArray solver. In this case, connect the gate inputs to PWM Capture blocks from the RT Box component library.

Switched

The power semiconductors are modelled as ideal switches controlled by instantaneous logical gate signals. A switch is turned on when the corresponding gate signal is non-zero. For compatibility with the Sub-cycle average configuration it is recommended to use the value \(1\) for non-zero gate signals.

The Switched configuration is not recommended for real-time simulations on the RT Box. It is intended for offline simulations that resolve each individual switching event and can serve as a reference for results obtained with the Sub-cycle average configuration.

Note

The voltage sources connected to the converter must not be short-circuited. Therefore, combinations of switching signals that cause shoot-through of DC links are not permitted. The corresponding restrictions are described under the Assertions parameter. Additionally, DC voltages across diodes must not be negative, as DC voltage clamping through diodes is not permitted.

Parameters

Configuration

Selects the component configuration. See the descriptions of Sub-cycle average and Switched above.

Semiconductor symbol

Use this setting to choose between IGBT and MOSFET for the symbol of the active semiconductor switches. This setting only affects the schematic representation and does not change the electrical behavior of the component.

Number of capacitors

Specifies how many capacitors and how many voltage levels the half bridge power module contains.

Assertions

If the Configuration is set to Sub-cycle average and this parameter is set to on, the block checks the duty-cycle gate input signals for overlapping relative on-times. It issues a Half-bridge shoot-through error if the following condition is met:

  • The sum of the gate signals for any checked switch pair exceeds \(1\). The checked pairs are \((S_1,S_n)\), \((S_2,S_{n-1})\), and so on, where \(S_1\) and \(S_n\) are connected to the outer DC bus terminals, \(S_2\) and \(S_{n-1}\) are connected to the next inner capacitor voltage level, etc.

Switch model (CPU code generation)

If the Configuration is set to Sub-cycle average, this parameter selects the switch model when CPU code is generated.

↳ Added in PLECS 4.4.