3-Phase T-Type Voltage Source Inverter

Purpose

3-phase T-type voltage source inverter with filter inductors, optimized for Real-Time Simulations on the RT Box.

Library

Electrical / Nanostep

Description

This component implements a 3-phase 3-level T-type voltage source inverter. It includes filter inductors on the AC side.

Both sides of the converter have current source behavior. The DC side must be connected directly to a capacitor or a voltage source.

The component offers two configurations:

Nanostep / Switched

The power semiconductors are modelled as ideal switches controlled by instantaneous logical gate signals. A switch is turned on when the corresponding gate signal is true.

In Nanostep / Switched configuration, C code generated from this component is suitable for real-time simulations on the RT Box, where it is executed on a Nanostep solver. In this case, connect the gate inputs to PWM Capture blocks from the RT Box component library.

The Nanostep implementation requires the DC and AC sides to be galvanically isolated. Any electrical connection between the two sides outside the component would therefore not reflect the actual current and voltage situation and should be avoided.

Sub-cycle average

Each gate input is controlled by a floating-point number with values between \(0\) and \(1\), representing the relative on-time of the corresponding semiconductor over one simulation step, as described in Sub-cycle Averaging.

In Sub-cycle average configuration, C code generated from this component is suitable for real-time simulations on the RT Box, where it is executed on the CPU or FlexArray solver. In this case, connect the gate inputs to PWM Capture blocks from the RT Box component library.

Note

This component has a Nanostep solver weight of \(3\), indicating that it occupies one entire Nanostep solver for Real-time Simulations on the RT Box.

Note

The voltage sources connected to the converter must not be short-circuited. Therefore, combinations of switching signals that cause shoot-through of DC links are not permitted. Additionally, DC voltages across diodes must not be negative, as DC voltage clamping through diodes is not permitted.

Parameters

Configuration

Selects the component configuration. See the descriptions of Nanostep / Switched and Sub-cycle average above.

Switch model (CPU code generation)

If the Configuration is set to Sub-cycle average, this parameter selects the switch model when CPU code is generated.

Semiconductor symbol

Use this setting to choose between IGBT and MOSFET for the symbol of the active semiconductor switches. This setting only affects the schematic representation and does not change the electrical behavior of the component.

Neutral-point connection

Specifies if the neutral-point switches are series connected with Common collector (drain for MOSFETs) or Common emitter (source for MOSFETs).

Inductance

A non-zero scalar or 3-element vector specifying the inductances \(\mathrm{L}\), in henries (\(\mathrm{H}\)).

Winding resistance

A non-zero scalar or 3-element vector specifying the winding resistances \(\mathrm{R_L}\), in ohms \((\Omega)\).

Assertions

When set to on, the block flags an error for combinations of gate signals that cause shoot-through.

Nanostep Probe Signals

See Fig. 255 for the probe signal positions.

Inductor currents

A vector containing the currents through the inductors \(\mathrm{L}\), in amperes \((\mathrm{A})\), defined positive in the direction of the arrow.

DC link currents

A vector containing the currents at the DC-link side converter terminals, in amperes \((\mathrm{A})\), defined positive in the direction of the arrow.

Gate signals

A vector for each phase containing the gate signals of the semiconductor switches.

Fig. 255 Probes for the 3-Phase T-Type Voltage Source Inverter

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↳ Added in PLECS 4.9.